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0a9b182ef7
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BAD CODE: testing that CI pipeline catches verilog issues
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2021-07-02 02:39:13 -06:00 |
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07c2fb570c
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BAD CODE: to test CI pipeline
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2021-07-02 02:38:01 -06:00 |
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e24d230f1a
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Update .gitlab-ci.yml file
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2021-07-02 08:35:22 +00:00 |
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efe2696313
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Update .gitlab-ci.yml file
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2021-07-02 08:33:53 +00:00 |
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04443b191a
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Update .gitlab-ci.yml file
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2021-07-02 08:33:02 +00:00 |
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f963054244
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Update .gitlab-ci.yml file
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2021-07-02 08:30:50 +00:00 |
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5d0a394b41
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Update .gitlab-ci.yml file
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2021-07-02 08:26:25 +00:00 |
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c1c7c13ce0
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Update .gitlab-ci.yml file
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2021-07-02 08:24:56 +00:00 |
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fd743338c9
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Update .gitlab-ci.yml file
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2021-07-02 08:22:30 +00:00 |
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f2ac820e7e
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Update .gitlab-ci.yml file
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2021-07-02 08:19:22 +00:00 |
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1184255fca
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Update .gitlab-ci.yml file
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2021-07-02 08:19:17 +00:00 |
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b2875388b2
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remove old sim file from xilinx toolchain
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2021-07-02 02:08:48 -06:00 |
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6f574abc9d
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clean up
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2021-07-02 02:07:22 -06:00 |
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e32e451e60
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update waveform view
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2021-07-02 02:03:32 -06:00 |
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5c59c97797
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build software project in same makefile as hardware project
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2021-07-02 02:03:32 -06:00 |
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4580631939
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clean up hdl directory
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2021-07-02 02:03:32 -06:00 |
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fc232b0d8b
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remove unnecessary stuff
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2021-07-02 02:03:32 -06:00 |
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efd4cb6e48
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build test code into build directory
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2021-07-02 02:03:32 -06:00 |
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180f05fb0a
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shift to iverilog + gtkwave for simulation
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2021-07-02 02:03:32 -06:00 |
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82283f01f4
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Add README.md
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2021-05-04 04:47:58 +00:00 |
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a6a8b68c3b
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untracked files
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2021-05-03 22:13:26 -06:00 |
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96c9a06589
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uncommitted changes
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2021-05-03 22:13:11 -06:00 |
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a2a85fd10b
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add test for immediate offsets for lw instruction
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2020-11-14 23:48:08 -07:00 |
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d58661e289
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add more extensive memory test
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2020-11-14 23:36:23 -07:00 |
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6d39c01740
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fix testbench so both load and store work
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2020-11-14 23:21:33 -07:00 |
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f0166f1954
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load (word only) appears to be working
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2020-11-14 23:13:24 -07:00 |
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4a25ca6def
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fix issue of jumping to address 0
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2020-11-14 23:04:24 -07:00 |
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caf9a6f4f7
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separate .text and .data for instruction and data memory
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2020-11-10 00:19:42 -07:00 |
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32d0a2dcaa
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display more data to simplify verification
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2020-11-09 23:38:22 -07:00 |
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21883dbd84
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passes quick test: bne, bge, bgeu
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2020-11-09 20:22:18 -07:00 |
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6e0d9c96a1
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passes quick test: beq, blt, bltu
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2020-11-09 20:01:25 -07:00 |
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06d0e07c61
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clean up some notes in test.S
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2020-11-07 00:54:50 -07:00 |
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f6c0fb7da1
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remove lots of nop
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2020-11-07 00:53:49 -07:00 |
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82cbaba7e5
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I think this properly stalls for all implemented instructions so I don't need nops
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2020-11-07 00:47:20 -07:00 |
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1290418aa3
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properly flushes pipeline after jump
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2020-11-06 23:18:37 -07:00 |
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c25b9bcb0f
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passes quick test: auipc
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2020-10-16 18:59:25 -06:00 |
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c98881c5d7
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passes quick test: slt, slti, sltu, sltiu
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2020-10-16 18:51:51 -06:00 |
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48c8b035bd
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add instruction decoder spreadsheet
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2020-10-16 18:26:05 -06:00 |
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52a28d4e47
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passes quick test: sll, srl, sra
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2020-10-16 18:25:10 -06:00 |
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913ffb3af6
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passes quick test: slli, srli, srai
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2020-10-11 23:36:11 -06:00 |
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46a0972803
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passes quick test: xori
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2020-10-11 23:09:08 -06:00 |
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bbaf6f9141
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passes quick test: ori
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2020-10-11 23:06:29 -06:00 |
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2c24c19a72
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passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
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2020-10-11 23:03:14 -06:00 |
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3fbd96ca27
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sub, and, or don't always work
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2020-10-03 13:49:14 -06:00 |
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18892acec9
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remove *.elf *.hex from git
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2020-09-27 18:40:29 -06:00 |
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24171412bd
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successfully using assembler to generate .hex rather than writing straight machine code
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2020-09-27 18:38:35 -06:00 |
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275f66bf24
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fix typo in core_tb.v assembly
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2020-09-27 18:07:12 -06:00 |
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99cdda0dd7
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uggh. now it doesn't track the submodule when I move it
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2020-09-27 18:06:35 -06:00 |
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6fc8195b27
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move assembly project
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2020-09-27 18:05:58 -06:00 |
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cd811470bb
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prevent git from getting mad about this submodule
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2020-09-27 18:05:30 -06:00 |
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