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brendanhaines
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cpu
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Brendan Haines
275f66bf24
fix typo in core_tb.v assembly
2020-09-27 18:07:12 -06:00
hdl
fix typo in core_tb.v assembly
2020-09-27 18:07:12 -06:00
sim
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
test
move assembly project
2020-09-27 18:05:58 -06:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
Description
RISC-V CPU
174
KiB
Languages
Verilog
44.4%
SystemVerilog
36.4%
Assembly
14.9%
Makefile
3.8%
Shell
0.4%
