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RISC-V CPU
8 Commits 2 Branches 0 Tags 172 KiB
Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
Shell 0.4%
18892acec9
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Brendan Haines 18892acec9 remove *.elf *.hex from git
2020-09-27 18:40:29 -06:00
hdl successfully using assembler to generate .hex rather than writing straight machine code 2020-09-27 18:38:35 -06:00
sim successfully using assembler to generate .hex rather than writing straight machine code 2020-09-27 18:38:35 -06:00
test remove *.elf *.hex from git 2020-09-27 18:40:29 -06:00
.gitignore initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
.gitmodules uggh. now it doesn't track the submodule when I move it 2020-09-27 18:06:35 -06:00
Makefile initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
pins.ucf initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
project.cfg initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00