Brendan Haines 2c24c19a72 passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link

2020-10-11 23:03:14 -06:00

hdl

passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link

2020-10-11 23:03:14 -06:00

sim

successfully using assembler to generate .hex rather than writing straight machine code

2020-09-27 18:38:35 -06:00

test

passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link

2020-10-11 23:03:14 -06:00

.gitignore

initial commit. Non-working due to newly added MEM backpressure signal

2020-09-27 16:04:16 -06:00

.gitmodules

uggh. now it doesn't track the submodule when I move it

2020-09-27 18:06:35 -06:00

Makefile

initial commit. Non-working due to newly added MEM backpressure signal

2020-09-27 16:04:16 -06:00

pins.ucf

initial commit. Non-working due to newly added MEM backpressure signal

2020-09-27 16:04:16 -06:00

project.cfg

passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link

2020-10-11 23:03:14 -06:00

Description

RISC-V CPU

525 KiB

Languages

Verilog 44.7%

SystemVerilog 36.6%

Assembly 15.1%

Makefile 3.5%