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brendanhaines
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cpu
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https://gitlab.com/brendanhaines/cpu.git
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2025-04-06 09:04:28 -06:00
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Brendan Haines
1290418aa3
properly flushes pipeline after jump
2020-11-06 23:18:37 -07:00
hdl
properly flushes pipeline after jump
2020-11-06 23:18:37 -07:00
sim
properly flushes pipeline after jump
2020-11-06 23:18:37 -07:00
test
properly flushes pipeline after jump
2020-11-06 23:18:37 -07:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
2020-10-11 23:03:14 -06:00
Description
RISC-V CPU
172
KiB
Languages
Verilog
44.4%
SystemVerilog
36.4%
Assembly
14.9%
Makefile
3.8%
Shell
0.4%
