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brendanhaines
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cpu
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Brendan Haines
3fbd96ca27
sub, and, or don't always work
2020-10-03 13:49:14 -06:00
hdl
sub, and, or don't always work
2020-10-03 13:49:14 -06:00
sim
successfully using assembler to generate .hex rather than writing straight machine code
2020-09-27 18:38:35 -06:00
test
sub, and, or don't always work
2020-10-03 13:49:14 -06:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
Description
RISC-V CPU
174
KiB
Languages
Verilog
44.4%
SystemVerilog
36.4%
Assembly
14.9%
Makefile
3.8%
Shell
0.4%
