This website requires JavaScript.
Explore
Help
Sign In
brendanhaines
/
cpu
Watch
1
Star
0
Fork
0
You've already forked cpu
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
21
Commits
2
Branches
0
Tags
06d0e07c612db030ea34e54fa13de841d4abbfe4
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Brendan Haines
06d0e07c61
clean up some notes in test.S
2020-11-07 00:54:50 -07:00
hdl
I think this properly stalls for all implemented instructions so I don't need nops
2020-11-07 00:47:20 -07:00
sim
I think this properly stalls for all implemented instructions so I don't need nops
2020-11-07 00:47:20 -07:00
test
clean up some notes in test.S
2020-11-07 00:54:50 -07:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
2020-10-11 23:03:14 -06:00
Description
RISC-V CPU
525
KiB
Languages
Verilog
44.7%
SystemVerilog
36.6%
Assembly
15.1%
Makefile
3.5%
