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brendanhaines
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cpu
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48c8b035bd068b14e0b718ce88c9e5764e4bb390
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Brendan Haines
48c8b035bd
add instruction decoder spreadsheet
2020-10-16 18:26:05 -06:00
hdl
passes quick test: sll, srl, sra
2020-10-16 18:25:10 -06:00
sim
passes quick test: sll, srl, sra
2020-10-16 18:25:10 -06:00
test
add instruction decoder spreadsheet
2020-10-16 18:26:05 -06:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
2020-10-11 23:03:14 -06:00
Description
RISC-V CPU
525
KiB
Languages
Verilog
44.7%
SystemVerilog
36.6%
Assembly
15.1%
Makefile
3.5%
