This website requires JavaScript.
Explore
Help
Sign In
brendanhaines
/
cpu
Watch
1
Star
0
Fork
0
You've already forked cpu
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
30
Commits
2
Branches
0
Tags
a2a85fd10b7c32f69816bbc43b9e267fc9825385
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Brendan Haines
a2a85fd10b
add test for immediate offsets for lw instruction
2020-11-14 23:48:08 -07:00
hdl
add more extensive memory test
2020-11-14 23:36:23 -07:00
sim
add more extensive memory test
2020-11-14 23:36:23 -07:00
test
add test for immediate offsets for lw instruction
2020-11-14 23:48:08 -07:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
2020-10-11 23:03:14 -06:00
Description
RISC-V CPU
174
KiB
Languages
Verilog
44.4%
SystemVerilog
36.4%
Assembly
14.9%
Makefile
3.8%
Shell
0.4%
