brendanhaines/cpu
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RISC-V CPU
31 Commits 2 Branches 0 Tags 172 KiB
Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
Shell 0.4%
96c9a06589
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Brendan Haines 96c9a06589 uncommitted changes
2021-05-03 22:13:11 -06:00
hdl add more extensive memory test 2020-11-14 23:36:23 -07:00
sim add more extensive memory test 2020-11-14 23:36:23 -07:00
test uncommitted changes 2021-05-03 22:13:11 -06:00
.gitignore initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
.gitmodules uggh. now it doesn't track the submodule when I move it 2020-09-27 18:06:35 -06:00
Makefile initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
pins.ucf initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
project.cfg passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link 2020-10-11 23:03:14 -06:00