mirror of
https://gitlab.com/brendanhaines/cpu.git
synced 2024-12-25 18:46:53 -07:00
update waveform view
This commit is contained in:
parent
5c59c97797
commit
e32e451e60
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@ -1,22 +1,172 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Fri Jul 2 06:48:14 2021
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[*] Fri Jul 2 08:01:39 2021
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[*]
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[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/hdl/core_tb.vcd"
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[dumpfile_mtime] "Fri Jul 2 06:46:26 2021"
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[dumpfile_size] 667859
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[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
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[dumpfile_mtime] "Fri Jul 2 07:58:09 2021"
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[dumpfile_size] 681929
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[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
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[timestart] 0
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[size] 1871 1025
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[pos] -1900 -2
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*0.000000 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[size] 1920 1052
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[pos] -1 -1
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*-20.000000 461000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] core_tb.
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[treeopen] core_tb.dut.
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[sst_width] 289
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[signals_width] 199
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[signals_width] 241
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[sst_expanded] 1
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[sst_vpaned_height] 301
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@200
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-TB
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@28
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core_tb.clk
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core_tb.reset
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@200
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-DUT
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@22
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core_tb.dut.\regfile[0][31:0]
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core_tb.dut.\regfile[1][31:0]
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core_tb.dut.\regfile[2][31:0]
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core_tb.dut.\regfile[3][31:0]
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core_tb.dut.\regfile[4][31:0]
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core_tb.dut.\regfile[5][31:0]
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core_tb.dut.\regfile[6][31:0]
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core_tb.dut.\regfile[7][31:0]
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core_tb.dut.\regfile[8][31:0]
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core_tb.dut.\regfile[9][31:0]
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core_tb.dut.\regfile[10][31:0]
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core_tb.dut.\regfile[11][31:0]
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core_tb.dut.\regfile[12][31:0]
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core_tb.dut.\regfile[13][31:0]
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core_tb.dut.\regfile[14][31:0]
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core_tb.dut.\regfile[15][31:0]
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core_tb.dut.\regfile[16][31:0]
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core_tb.dut.\regfile[17][31:0]
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core_tb.dut.\regfile[18][31:0]
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core_tb.dut.\regfile[19][31:0]
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core_tb.dut.\regfile[20][31:0]
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core_tb.dut.\regfile[21][31:0]
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core_tb.dut.\regfile[22][31:0]
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core_tb.dut.\regfile[23][31:0]
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@c00022
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core_tb.dut.\regfile[24][31:0]
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@28
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(0)core_tb.dut.\regfile[24][31:0]
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(1)core_tb.dut.\regfile[24][31:0]
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(2)core_tb.dut.\regfile[24][31:0]
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(3)core_tb.dut.\regfile[24][31:0]
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(4)core_tb.dut.\regfile[24][31:0]
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(5)core_tb.dut.\regfile[24][31:0]
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(6)core_tb.dut.\regfile[24][31:0]
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(7)core_tb.dut.\regfile[24][31:0]
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(8)core_tb.dut.\regfile[24][31:0]
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(9)core_tb.dut.\regfile[24][31:0]
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(10)core_tb.dut.\regfile[24][31:0]
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(11)core_tb.dut.\regfile[24][31:0]
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(12)core_tb.dut.\regfile[24][31:0]
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(13)core_tb.dut.\regfile[24][31:0]
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(14)core_tb.dut.\regfile[24][31:0]
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(15)core_tb.dut.\regfile[24][31:0]
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(16)core_tb.dut.\regfile[24][31:0]
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(17)core_tb.dut.\regfile[24][31:0]
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(18)core_tb.dut.\regfile[24][31:0]
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(19)core_tb.dut.\regfile[24][31:0]
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(20)core_tb.dut.\regfile[24][31:0]
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(21)core_tb.dut.\regfile[24][31:0]
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(22)core_tb.dut.\regfile[24][31:0]
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(23)core_tb.dut.\regfile[24][31:0]
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(24)core_tb.dut.\regfile[24][31:0]
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(25)core_tb.dut.\regfile[24][31:0]
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(26)core_tb.dut.\regfile[24][31:0]
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(27)core_tb.dut.\regfile[24][31:0]
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(28)core_tb.dut.\regfile[24][31:0]
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(29)core_tb.dut.\regfile[24][31:0]
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(30)core_tb.dut.\regfile[24][31:0]
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(31)core_tb.dut.\regfile[24][31:0]
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@1401200
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-group_end
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@22
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core_tb.dut.\regfile[25][31:0]
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core_tb.dut.\regfile[26][31:0]
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core_tb.dut.\regfile[27][31:0]
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@23
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core_tb.dut.\regfile[28][31:0]
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@22
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core_tb.dut.\regfile[29][31:0]
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core_tb.dut.\regfile[30][31:0]
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core_tb.dut.\regfile[31][31:0]
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@200
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-
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@c00022
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core_tb.dut.r_if_pc[31:0]
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@28
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(0)core_tb.dut.r_if_pc[31:0]
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(1)core_tb.dut.r_if_pc[31:0]
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(2)core_tb.dut.r_if_pc[31:0]
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(3)core_tb.dut.r_if_pc[31:0]
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(4)core_tb.dut.r_if_pc[31:0]
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(5)core_tb.dut.r_if_pc[31:0]
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(6)core_tb.dut.r_if_pc[31:0]
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(7)core_tb.dut.r_if_pc[31:0]
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(8)core_tb.dut.r_if_pc[31:0]
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(9)core_tb.dut.r_if_pc[31:0]
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(10)core_tb.dut.r_if_pc[31:0]
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(11)core_tb.dut.r_if_pc[31:0]
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(12)core_tb.dut.r_if_pc[31:0]
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(13)core_tb.dut.r_if_pc[31:0]
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(14)core_tb.dut.r_if_pc[31:0]
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(15)core_tb.dut.r_if_pc[31:0]
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(16)core_tb.dut.r_if_pc[31:0]
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(17)core_tb.dut.r_if_pc[31:0]
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(18)core_tb.dut.r_if_pc[31:0]
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(19)core_tb.dut.r_if_pc[31:0]
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(20)core_tb.dut.r_if_pc[31:0]
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(21)core_tb.dut.r_if_pc[31:0]
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(22)core_tb.dut.r_if_pc[31:0]
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(23)core_tb.dut.r_if_pc[31:0]
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(24)core_tb.dut.r_if_pc[31:0]
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(25)core_tb.dut.r_if_pc[31:0]
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(26)core_tb.dut.r_if_pc[31:0]
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(27)core_tb.dut.r_if_pc[31:0]
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(28)core_tb.dut.r_if_pc[31:0]
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(29)core_tb.dut.r_if_pc[31:0]
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(30)core_tb.dut.r_if_pc[31:0]
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(31)core_tb.dut.r_if_pc[31:0]
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@1401200
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-group_end
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@200
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-
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@28
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core_tb.dut.r_id_valid
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@22
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core_tb.dut.r_id_pc[31:0]
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core_tb.dut.r_id_inst[31:0]
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@200
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-
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@28
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core_tb.dut.r_ex_valid
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@22
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core_tb.dut.r_ex_pc[31:0]
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core_tb.dut.r_ex_inst[31:0]
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@24
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core_tb.dut.r_ex_rs1[4:0]
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core_tb.dut.r_ex_rs2[4:0]
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core_tb.dut.r_ex_rd[4:0]
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@22
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core_tb.dut.r_ex_aluop[3:0]
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@28
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core_tb.dut.r_ex_jump
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core_tb.dut.r_ex_branch
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core_tb.dut.r_ex_branch_pol
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core_tb.dut.r_ex_load
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core_tb.dut.r_ex_store
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@200
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-
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@22
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core_tb.dut.r_mem_pc[31:0]
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@200
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-
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@22
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core_tb.dut.r_wb_pc[31:0]
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[pattern_trace] 1
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[pattern_trace] 0
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@ -3,9 +3,13 @@
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module core_tb();
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initial $timeformat(-9, 2, " ns", 20);
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initial begin
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initial begin: dump
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integer i;
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$dumpfile("core_tb.vcd");
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$dumpvars(0);
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$dumpvars(0, core_tb);
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for (i=0; i<32; i=i+1) begin
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$dumpvars(0, dut.regfile[i]);
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end
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end
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wire dummy_out;
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