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brendanhaines
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cpu
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99cdda0dd70b65b111a1b705f0ad12f835acd4ed
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Brendan Haines
99cdda0dd7
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
hdl
add test assembly file
2020-09-27 18:04:08 -06:00
sim
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
test
move assembly project
2020-09-27 18:05:58 -06:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
Description
RISC-V CPU
525
KiB
Languages
Verilog
44.7%
SystemVerilog
36.6%
Assembly
15.1%
Makefile
3.5%
