This website requires JavaScript.
Explore
Help
Sign In
brendanhaines
/
cpu
Watch
1
Star
0
Fork
0
You've already forked cpu
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
24
Commits
2
Branches
0
Tags
32d0a2dcaad8f171ef54d75a6a7ffb5cd6814569
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Brendan Haines
32d0a2dcaa
display more data to simplify verification
2020-11-09 23:38:22 -07:00
hdl
display more data to simplify verification
2020-11-09 23:38:22 -07:00
sim
passes quick test: beq, blt, bltu
2020-11-09 20:01:25 -07:00
test
passes quick test: bne, bge, bgeu
2020-11-09 20:22:18 -07:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
2020-10-11 23:03:14 -06:00
Description
RISC-V CPU
174
KiB
Languages
Verilog
44.4%
SystemVerilog
36.4%
Assembly
14.9%
Makefile
3.8%
Shell
0.4%
