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brendanhaines
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cpu
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caf9a6f4f7a40f725dc57a3f675434aaa265e1b8
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Brendan Haines
caf9a6f4f7
separate .text and .data for instruction and data memory
2020-11-10 00:19:42 -07:00
hdl
separate .text and .data for instruction and data memory
2020-11-10 00:19:42 -07:00
sim
passes quick test: beq, blt, bltu
2020-11-09 20:01:25 -07:00
test
separate .text and .data for instruction and data memory
2020-11-10 00:19:42 -07:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
2020-10-11 23:03:14 -06:00
Description
RISC-V CPU
174
KiB
Languages
Verilog
44.4%
SystemVerilog
36.4%
Assembly
14.9%
Makefile
3.8%
Shell
0.4%
