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cpu
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Brendan Haines
6d39c01740
fix testbench so both load and store work
2020-11-14 23:21:33 -07:00
hdl
fix testbench so both load and store work
2020-11-14 23:21:33 -07:00
sim
fix testbench so both load and store work
2020-11-14 23:21:33 -07:00
test
load (word only) appears to be working
2020-11-14 23:13:24 -07:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
uggh. now it doesn't track the submodule when I move it
2020-09-27 18:06:35 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
2020-10-11 23:03:14 -06:00
Description
RISC-V CPU
525
KiB
Languages
Verilog
44.7%
SystemVerilog
36.6%
Assembly
15.1%
Makefile
3.5%
