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brendanhaines
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cpu
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cd811470bb908e528a3f29a46d8c04d85b07c4b7
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Brendan Haines
cd811470bb
prevent git from getting mad about this submodule
2020-09-27 18:05:30 -06:00
asm
prevent git from getting mad about this submodule
2020-09-27 18:05:30 -06:00
hdl
add test assembly file
2020-09-27 18:04:08 -06:00
sim
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
add test assembly file
2020-09-27 18:04:08 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
Description
RISC-V CPU
525
KiB
Languages
Verilog
44.7%
SystemVerilog
36.6%
Assembly
15.1%
Makefile
3.5%
