RISC-V CPU
Go to file
2022-12-07 20:03:13 -07:00
.vscode working assertion lib 2022-12-01 01:03:23 -07:00
docs move some stuff 2021-09-09 00:56:45 -06:00
lib fix rdata output 2022-12-07 20:03:13 -07:00
other_projects add start of JTAG TAP 2021-09-09 00:06:57 -06:00
riscv-gnu-toolchain@96d9f40c9d add correct riscv toolchain. Build takes forever so I'll probably add the binaries later 2022-11-19 18:40:37 -07:00
src restructure testbenches and common code 2022-12-01 00:45:57 -07:00
tests remove reference to old axil bridge location 2022-12-01 01:14:01 -07:00
.gitignore add correct riscv toolchain. Build takes forever so I'll probably add the binaries later 2022-11-19 18:40:37 -07:00
.gitlab-ci.yml update .gitlab-ci.yml 2022-12-01 02:17:51 -07:00
.gitmodules add correct riscv toolchain. Build takes forever so I'll probably add the binaries later 2022-11-19 18:40:37 -07:00
README.md comments n stuff 2022-11-19 21:24:08 -07:00
setup.sh add correct riscv toolchain. Build takes forever so I'll probably add the binaries later 2022-11-19 18:40:37 -07:00

pipeline status

RISC-V CPU

Short Term To Do:

  • add stalls for memory access
  • use AXI for memory access (depends on AXIL memory module for test)
  • add tests for non-pipelined case
  • get C working (may depend on memory stalls)

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, (or 128?) bit word size
  • floating point
  • multiplication
  • division
  • instruction and data caches
  • JTAG debug probe

Installation

Run setup.sh to install GCC

Resources