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Code Issues Packages Projects Releases Wiki Activity
RISC-V CPU
27 Commits 2 Branches 0 Tags 172 KiB
Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
Shell 0.4%
f0166f1954
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Brendan Haines f0166f1954 load (word only) appears to be working
2020-11-14 23:13:24 -07:00
hdl load (word only) appears to be working 2020-11-14 23:13:24 -07:00
sim load (word only) appears to be working 2020-11-14 23:13:24 -07:00
test load (word only) appears to be working 2020-11-14 23:13:24 -07:00
.gitignore initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
.gitmodules uggh. now it doesn't track the submodule when I move it 2020-09-27 18:06:35 -06:00
Makefile initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
pins.ucf initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
project.cfg passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link 2020-10-11 23:03:14 -06:00