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fix testbench so both load and store work

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This commit is contained in:
Brendan Haines 2020-11-14 23:21:33 -07:00
parent f0166f1954
commit 6d39c01740
2 changed files with 36 additions and 4 deletions
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14
hdl/tb/core_tb.v
View File

@ -9,6 +9,8 @@ wire dummy_out;
localparam MEM_INST_LENGTH = 256; // words
localparam MEM_DATA_LENGTH = 256; // words
localparam MEM_DATA_BASE = 32'h00100000;
localparam INST_NOP = 32'h00000013; // nop
localparam DATA_DEFAULT = 32'h00000000;
localparam DATA_INVALID = 32'hdeadbeef;
@ -140,10 +142,17 @@ core dut(
// .WB_RREADY()
// );
wire [31:0] mem_data_idx = mem_data_addr >> 2;
always @(posedge clk) begin
wire [31:0] mem_data_idx = (mem_data_addr - MEM_DATA_BASE) >> 2;
always @(*) begin
if (mem_data_idx < MEM_DATA_LENGTH) begin
mem_data_rdata = mem_data[mem_data_idx];
end else begin
mem_data_rdata = DATA_INVALID;
end
end
always @(posedge clk) begin
if (mem_data_idx < MEM_DATA_LENGTH) begin
if (mem_data_we) begin
if (mem_data_wmask[0]) begin
mem_data[mem_data_idx][7:0] <= mem_data_wdata[7:0];
@ -159,7 +168,6 @@ always @(posedge clk) begin
end
end
end else begin
mem_data_rdata = DATA_INVALID;
// ignore illegal writes
end
end

26
sim/core_tb.wcfg
View File

@ -10,7 +10,7 @@
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="9" />
<WVObjectSize size="14" />
<wvobject fp_name="/core_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
@ -24,6 +24,30 @@
<obj_property name="ObjectShortName">mem_data[0:255,31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/mem_data_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_data_addr[31:0]</obj_property>
<obj_property name="ObjectShortName">mem_data_addr[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/mem_data_idx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_data_idx[31:0]</obj_property>
<obj_property name="ObjectShortName">mem_data_idx[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/mem_data_rdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_data_rdata[31:0]</obj_property>
<obj_property name="ObjectShortName">mem_data_rdata[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/mem_data_wdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_data_wdata[31:0]</obj_property>
<obj_property name="ObjectShortName">mem_data_wdata[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/mem_data_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_data_we</obj_property>
<obj_property name="ObjectShortName">mem_data_we</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/dut/regfile" type="array" db_ref_id="1">
<obj_property name="ElementShortName">regfile[0:31,31:0]</obj_property>
<obj_property name="ObjectShortName">regfile[0:31,31:0]</obj_property>