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6b0a72d516
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add a basic diagram
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2021-07-03 21:18:03 -06:00 |
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8decf52443
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make mem_data_rvalid a reg in tb
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2021-07-03 21:17:42 -06:00 |
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cc4101c1f8
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prevent simulation from printing all writes to regfile
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2021-07-03 21:02:48 -06:00 |
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34dc20f115
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fix intentional test.S error
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2021-07-03 21:01:29 -06:00 |
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c03866f56a
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BAD CODE: check pipeline's ability to detect test script failure
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2021-07-03 21:00:34 -06:00 |
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e3c52db637
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make sim will now fail if test hits fail state
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2021-07-03 20:59:03 -06:00 |
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d4ed4ec2bc
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add ability to wait for memory writes
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2021-07-03 19:39:22 -06:00 |
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dd8bad9610
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Fix .gitlab-ci.yml file
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2021-07-04 00:52:26 +00:00 |
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bd6c60fe92
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Fix .gitlab-ci.yml
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2021-07-04 00:50:25 +00:00 |
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9707698281
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cleanup
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2021-07-03 18:48:07 -06:00 |
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2225ccd311
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trying to also use .c files. Not yet working but doesn't break .as files
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2021-07-02 05:16:30 -06:00 |
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b79c572a22
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tweak makefile
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2021-07-02 04:58:58 -06:00 |
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c0852697df
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remove outdated comment
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2021-07-02 04:52:48 -06:00 |
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5e87ea0c75
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fix loading of sectios other than .text and get rid of massive sed chain for .hex generation
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2021-07-02 04:47:40 -06:00 |
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9031b5b4c5
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working load/store word with byte addressed memory
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2021-07-02 04:32:25 -06:00 |
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35423ce4af
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works with 8bit addressed memory (rather than word addressed)
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2021-07-02 04:22:33 -06:00 |
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57e745b336
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more clean up and reorganization from memory restructuring
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2021-07-02 03:28:21 -06:00 |
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69e4ea9204
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clean up core_tb.v a little
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2021-07-02 03:20:38 -06:00 |
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07d317eb6e
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add trailing NOP instructions so non-initialized memory doesn't cause issues
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2021-07-02 03:14:37 -06:00 |
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9ff977c1be
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partially working with common address space. loading of .data section has been disabled
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2021-07-02 03:11:50 -06:00 |
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17a95b58c8
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fix the code issues I just introduced
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2021-07-02 02:39:43 -06:00 |
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0a9b182ef7
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BAD CODE: testing that CI pipeline catches verilog issues
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2021-07-02 02:39:13 -06:00 |
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07c2fb570c
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BAD CODE: to test CI pipeline
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2021-07-02 02:38:01 -06:00 |
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e24d230f1a
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Update .gitlab-ci.yml file
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2021-07-02 08:35:22 +00:00 |
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efe2696313
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Update .gitlab-ci.yml file
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2021-07-02 08:33:53 +00:00 |
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04443b191a
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Update .gitlab-ci.yml file
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2021-07-02 08:33:02 +00:00 |
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f963054244
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Update .gitlab-ci.yml file
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2021-07-02 08:30:50 +00:00 |
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5d0a394b41
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Update .gitlab-ci.yml file
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2021-07-02 08:26:25 +00:00 |
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c1c7c13ce0
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Update .gitlab-ci.yml file
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2021-07-02 08:24:56 +00:00 |
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fd743338c9
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Update .gitlab-ci.yml file
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2021-07-02 08:22:30 +00:00 |
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f2ac820e7e
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Update .gitlab-ci.yml file
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2021-07-02 08:19:22 +00:00 |
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1184255fca
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Update .gitlab-ci.yml file
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2021-07-02 08:19:17 +00:00 |
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b2875388b2
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remove old sim file from xilinx toolchain
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2021-07-02 02:08:48 -06:00 |
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6f574abc9d
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clean up
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2021-07-02 02:07:22 -06:00 |
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e32e451e60
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update waveform view
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2021-07-02 02:03:32 -06:00 |
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5c59c97797
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build software project in same makefile as hardware project
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2021-07-02 02:03:32 -06:00 |
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4580631939
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clean up hdl directory
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2021-07-02 02:03:32 -06:00 |
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fc232b0d8b
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remove unnecessary stuff
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2021-07-02 02:03:32 -06:00 |
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efd4cb6e48
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build test code into build directory
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2021-07-02 02:03:32 -06:00 |
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180f05fb0a
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shift to iverilog + gtkwave for simulation
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2021-07-02 02:03:32 -06:00 |
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82283f01f4
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Add README.md
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2021-05-04 04:47:58 +00:00 |
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a6a8b68c3b
|
untracked files
|
2021-05-03 22:13:26 -06:00 |
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96c9a06589
|
uncommitted changes
|
2021-05-03 22:13:11 -06:00 |
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a2a85fd10b
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add test for immediate offsets for lw instruction
|
2020-11-14 23:48:08 -07:00 |
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d58661e289
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add more extensive memory test
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2020-11-14 23:36:23 -07:00 |
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6d39c01740
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fix testbench so both load and store work
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2020-11-14 23:21:33 -07:00 |
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f0166f1954
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load (word only) appears to be working
|
2020-11-14 23:13:24 -07:00 |
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4a25ca6def
|
fix issue of jumping to address 0
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2020-11-14 23:04:24 -07:00 |
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caf9a6f4f7
|
separate .text and .data for instruction and data memory
|
2020-11-10 00:19:42 -07:00 |
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32d0a2dcaa
|
display more data to simplify verification
|
2020-11-09 23:38:22 -07:00 |
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