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make mem_data_rvalid a reg in tb

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This commit is contained in:
Brendan Haines 2021-07-03 21:17:42 -06:00
parent cc4101c1f8
commit 8decf52443
1 changed files with 3 additions and 2 deletions
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5
hdl/tb/core_tb.v
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@ -48,9 +48,10 @@ wire [31:0] mem_data_wdata;
wire [3:0] mem_data_wmask;
wire mem_data_we;
reg mem_data_wready;
wire mem_data_rvalid = 1'b1;
reg mem_data_rvalid;
always @(*) begin
always @(mem_data_addr) begin
mem_data_rvalid = 1'b1;
if (mem_data_addr < MEM_LENGTH - 3) begin
mem_data_rdata[ 7: 0] = mem[mem_data_addr+0];
if (mem_data_addr[0] == 0) begin