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prevent simulation from printing all writes to regfile

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Brendan Haines 2021-07-03 21:02:48 -06:00
parent 34dc20f115
commit cc4101c1f8
1 changed files with 1 additions and 1 deletions
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hdl/core.v
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@ -546,7 +546,7 @@ always @(posedge clk) begin: pipeline_update
// TODO: should I write if s_wb_stall=1?
if (r_wb_rd != 0 && s_wb_write && r_wb_valid) begin
regfile[r_wb_rd] <= s_wb_data;
$display("%0t:\tPC=0x%h\tx%02d=0x%h", $time, r_id_pc, r_wb_rd, s_wb_data);
// $display("%0t:\tPC=0x%h\tx%02d=0x%h", $time, r_id_pc, r_wb_rd, s_wb_data);
end
end
end