RISC-V CPU
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hdl working load/store word with byte addressed memory 2021-07-02 04:32:25 -06:00
test works with 8bit addressed memory (rather than word addressed) 2021-07-02 04:22:33 -06:00
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Makefile working load/store word with byte addressed memory 2021-07-02 04:32:25 -06:00
project.cfg passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link 2020-10-11 23:03:14 -06:00
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RISC-V CPU

Harvard architecture

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, or 128 bit word size
  • floating point support
  • multiplication
  • division
  • instruction and data caches