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https://gitlab.com/brendanhaines/cpu.git
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works with 8bit addressed memory (rather than word addressed)
This commit is contained in:
parent
57e745b336
commit
35423ce4af
15
Makefile
15
Makefile
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@ -37,13 +37,16 @@ $(BUILD_DIR)/%.o: test/%.c | $(BUILD_DIR)
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$(BUILD_DIR)/%.elf: test/%.ld $(BUILD_DIR)/%.o | $(BUILD_DIR)
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$(LD) $(LDFLAGS) $^ -o $@
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$(BUILD_DIR)/text.hex: $(BUILD_DIR)/test.elf
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riscv64-linux-gnu-objdump -s $^ | sed -n '/.text/,$$p' | tail -n+2 | sed -n '/.data/,$$!p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' | sed 's/^\(..\)\(..\)\(..\)\(..\)/\4\3\2\1/' > $@
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$(BUILD_DIR)/test.hex: $(BUILD_DIR)/test.elf
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# riscv64-linux-gnu-objdump -s $^ | sed -n '/.text/,$$p' | tail -n+2 | sed -n '/.data/,$$!p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' | sed 's/^\(..\)\(..\)\(..\)\(..\)/\4\3\2\1/' > $@
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riscv64-linux-gnu-objdump -s $^ | sed -n '/.text/,$$p' | tail -n+2 | sed -n '/.data/,$$!p' | cut -f3-6 -d ' ' | sed 's/ //g' | sed 's/\(..\)/\1 /g' > $@
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cat $@
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# riscv64-linux-gnu-objdump -s test.elf | sed -n '/Contents of section /,$p' | tail -n+2 | sed '/Contents of section .data/d' | cut -f2-6 -d ' ' | sed 's/./&:/4' | sed 's/./0x&/1' | sed 's/^[ \t]*//;s/[ \t]*$//' | sed 's/ /\n/g'
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# riscv64-linux-gnu-objdump -s test.elf | sed -n '/Contents of section /,$p' | tail -n+2 | sed '/Contents of section .data/d' | cut -f2-6 -d ' ' | sed 's/./&:/4' | sed 's/./0x&/1' | sed 's/^[ \t]*//;s/[ \t]*$//' | sed 's/./& /10' | sed 's/./& /13' | sed 's/./& /16' | sed 's/./& /22' | sed 's/./& /25' | sed 's/./& /28' | sed 's/./& /34' | sed 's/./& /37' | sed 's/./& /40' | sed 's/./& /46' | sed 's/./& /49' | sed 's/./& /52' | sed 's/ /\n/g'
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# $(BUILD_DIR)/data.hex: $(BUILD_DIR)/test.elf
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# riscv64-linux-gnu-objdump -s $^ | sed -n '/.data/,$$p' | tail -n+2 | sed -n '/.bss/,$$!p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' | sed 's/^\(..\)\(..\)\(..\)\(..\)/\4\3\2\1/' > $@
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$(BUILD_DIR)/data.hex: $(BUILD_DIR)/test.elf
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riscv64-linux-gnu-objdump -s $^ | sed -n '/.data/,$$p' | tail -n+2 | sed -n '/.bss/,$$!p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' | sed 's/^\(..\)\(..\)\(..\)\(..\)/\4\3\2\1/' > $@
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sim: $(BUILD_DIR)/tb.out $(BUILD_DIR)/text.hex $(BUILD_DIR)/data.hex
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sim: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
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cd $(BUILD_DIR) && ./tb.out
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@ -1,15 +1,15 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Fri Jul 2 09:22:29 2021
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[*] Fri Jul 2 10:10:54 2021
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[*]
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[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
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[dumpfile_mtime] "Fri Jul 2 09:19:55 2021"
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[dumpfile_size] 709401
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[dumpfile_mtime] "Fri Jul 2 10:09:55 2021"
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[dumpfile_size] 53841
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[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
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[timestart] 0
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[size] 1920 1052
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[pos] -1 -1
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*-20.000000 438000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-13.000000 12780 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] core_tb.
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[treeopen] core_tb.dut.
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[sst_width] 289
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@ -105,7 +105,6 @@ core_tb.dut.\regfile[27][31:0]
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core_tb.dut.\regfile[28][31:0]
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core_tb.dut.\regfile[29][31:0]
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core_tb.dut.\regfile[30][31:0]
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@23
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core_tb.dut.\regfile[31][31:0]
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@200
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-
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@ -153,6 +152,11 @@ core_tb.dut.r_id_valid
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@22
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core_tb.dut.r_id_pc[31:0]
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core_tb.dut.r_id_inst[31:0]
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core_tb.dut.s_id_immed_btype[31:0]
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core_tb.dut.s_id_immed_itype[31:0]
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core_tb.dut.s_id_immed_jtype[31:0]
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core_tb.dut.s_id_immed_stype[31:0]
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core_tb.dut.s_id_immed_utype[31:0]
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@200
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-
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@28
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@ -165,6 +169,10 @@ core_tb.dut.r_ex_rs1[4:0]
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core_tb.dut.r_ex_rs2[4:0]
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core_tb.dut.r_ex_rd[4:0]
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@22
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core_tb.dut.r_ex_s1[31:0]
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@23
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core_tb.dut.r_ex_s2[31:0]
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@22
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core_tb.dut.r_ex_aluop[3:0]
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@28
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core_tb.dut.r_ex_jump
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@ -16,18 +16,27 @@ reg clk, reset;
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wire dummy_out;
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// Memory Parameters
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localparam MEM_ROM_LENGTH = 2048 >> 2; // words
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localparam MEM_LENGTH = MEM_ROM_LENGTH + 2048 >> 2; // words
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localparam MEM_ROM_LENGTH = 2048; // bytes
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localparam MEM_LENGTH = MEM_ROM_LENGTH + 2048; // bytes
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localparam DATA_INVALID = 32'hdeadbeef;
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// Memory
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reg [31:0] mem [0:MEM_LENGTH-1];
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initial $readmemh("text.hex", mem);
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reg [7:0] mem [0:MEM_LENGTH-1];
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initial $readmemh("test.hex", mem);
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// Instruction Memory
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wire [31:0] mem_inst_addr;
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wire [31:0] mem_inst_idx = mem_inst_addr >> 2;
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wire [31:0] mem_inst_data = mem_inst_idx < MEM_LENGTH ? mem[mem_inst_idx] : DATA_INVALID;
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reg [31:0] mem_inst_data;
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always @(*) begin
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if (mem_inst_addr < MEM_LENGTH - 3) begin
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mem_inst_data[ 7: 0] = mem[mem_inst_addr+0];
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mem_inst_data[15: 8] = mem[mem_inst_addr+1];
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mem_inst_data[23:16] = mem[mem_inst_addr+2];
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mem_inst_data[31:24] = mem[mem_inst_addr+3];
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end else begin
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mem_inst_data = DATA_INVALID;
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end
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end
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// Data memory
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wire [31:0] mem_data_addr;
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@ -37,26 +46,26 @@ wire [31:0] mem_data_wdata;
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wire [3:0] mem_data_wmask;
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wire mem_data_we;
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always @(posedge clk) begin
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if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
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if (mem_data_we) begin
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if (mem_data_wmask[0]) begin
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mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
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end
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if (mem_data_wmask[1]) begin
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mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
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end
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if (mem_data_wmask[2]) begin
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mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
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end
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if (mem_data_wmask[3]) begin
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mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
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end
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end
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end else begin
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// ignore illegal writes
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end
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end
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// always @(posedge clk) begin
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// if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
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// if (mem_data_we) begin
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// if (mem_data_wmask[0]) begin
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// mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
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// end
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// if (mem_data_wmask[1]) begin
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// mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
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// end
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// if (mem_data_wmask[2]) begin
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// mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
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// end
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// if (mem_data_wmask[3]) begin
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// mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
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// end
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// end
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// end else begin
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// // ignore illegal writes
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// end
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// end
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// Main control
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1
test/.gitignore
vendored
1
test/.gitignore
vendored
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@ -1,3 +1,4 @@
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elf2hex
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*.elf
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*.hex
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*.~lock*
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@ -373,7 +373,7 @@ test_jalr:
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someint:
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.word 0xfedcba98
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someint16:
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.byte 0x1122
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.hword 0x1122
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someint8:
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.byte 0xaa
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anotherint8:
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