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RISC-V CPU
73 Commits 2 Branches 0 Tags 172 KiB
Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
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Brendan Haines 6b0a72d516 add a basic diagram
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documentation add a basic diagram 2021-07-03 21:18:03 -06:00
hdl make mem_data_rvalid a reg in tb 2021-07-03 21:17:42 -06:00
test fix intentional test.S error 2021-07-03 21:01:29 -06:00
.gitignore initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
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README.md

RISC-V CPU

Harvard architecture

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, or 128 bit word size
  • floating point support
  • multiplication
  • division
  • instruction and data caches