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RISC-V CPU
71 Commits 2 Branches 0 Tags 172 KiB
Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
Shell 0.4%
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Brendan Haines cc4101c1f8 prevent simulation from printing all writes to regfile
2021-07-03 21:02:48 -06:00
hdl prevent simulation from printing all writes to regfile 2021-07-03 21:02:48 -06:00
test fix intentional test.S error 2021-07-03 21:01:29 -06:00
.gitignore initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
.gitlab-ci.yml Fix .gitlab-ci.yml file 2021-07-04 00:52:26 +00:00
Makefile make sim will now fail if test hits fail state 2021-07-03 20:59:03 -06:00
README.md Add README.md 2021-05-04 04:47:58 +00:00

README.md

RISC-V CPU

Harvard architecture

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, or 128 bit word size
  • floating point support
  • multiplication
  • division
  • instruction and data caches