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RISC-V CPU
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Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
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Brendan Haines e3c52db637 make sim will now fail if test hits fail state
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test make sim will now fail if test hits fail state 2021-07-03 20:59:03 -06:00
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Makefile make sim will now fail if test hits fail state 2021-07-03 20:59:03 -06:00
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README.md

RISC-V CPU

Harvard architecture

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, or 128 bit word size
  • floating point support
  • multiplication
  • division
  • instruction and data caches