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RISC-V CPU
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Assembly 14.9%
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Brendan Haines 9707698281 cleanup
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hdl fix loading of sectios other than .text and get rid of massive sed chain for .hex generation 2021-07-02 04:47:40 -06:00
test cleanup 2021-07-03 18:48:07 -06:00
.gitignore initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00
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README.md

RISC-V CPU

Harvard architecture

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, or 128 bit word size
  • floating point support
  • multiplication
  • division
  • instruction and data caches