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51103c378d
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update comment
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2023-01-23 18:26:14 -07:00 |
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71bc903f14
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ignore overrun at end of skidbuffer test
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2022-12-28 22:24:55 -07:00 |
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3b476cfc32
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update gtkw paths
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2022-12-28 22:10:18 -07:00 |
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02db181281
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comment
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2022-12-28 22:07:28 -07:00 |
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f8c7460b29
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fix rdata output
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2022-12-07 20:03:13 -07:00 |
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2c19633fb5
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update .gitlab-ci.yml
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2022-12-01 02:17:51 -07:00 |
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e264602c1b
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Log levels are great but need more than one bit. oops
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2022-12-01 02:12:27 -07:00 |
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d3844129d3
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assert now catches X properly
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2022-12-01 02:09:51 -07:00 |
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cb7fbe84a5
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why does X look like 0 in my assertion for rdata?
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2022-12-01 02:04:17 -07:00 |
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c63a025615
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remove reference to old axil bridge location
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2022-12-01 01:14:01 -07:00 |
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e301d2c4d2
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move axil bridge
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2022-12-01 01:13:23 -07:00 |
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5d3d9b222f
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formatting
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2022-12-01 01:07:15 -07:00 |
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f12d3be0bd
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update makefile
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2022-12-01 01:05:39 -07:00 |
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38a91579ec
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working assertion lib
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2022-12-01 01:03:23 -07:00 |
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ebc3b22ac7
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restructure testbenches and common code
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2022-12-01 00:45:57 -07:00 |
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a2b0b2a709
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add skidbuffer. Untested
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2022-11-19 23:41:15 -07:00 |
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f770ad28c7
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comments n stuff
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2022-11-19 21:24:08 -07:00 |
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c6b68bb555
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Update .gitlab-ci.yml
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2022-11-19 21:23:07 -07:00 |
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249cf34339
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add bh_asserts.sv. Untested
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2022-11-19 18:41:50 -07:00 |
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449efd3c3c
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use systemverilog 2012 for simulation
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2022-11-19 18:41:25 -07:00 |
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8055444b99
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add correct riscv toolchain. Build takes forever so I'll probably add the binaries later
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2022-11-19 18:40:37 -07:00 |
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c1ec8520be
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implement axi-lite to wishbone bridge. Untested
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2022-11-19 18:37:35 -07:00 |
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03828419a9
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add linting in vscode
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2022-11-19 16:27:52 -07:00 |
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0fea83e14c
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update .gitlab-ci.yml
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2022-01-27 21:47:20 -07:00 |
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12e3078c2a
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should fix CI after moving tests
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2021-09-09 01:06:19 -06:00 |
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2d69722cb1
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rename testbench to tests
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2021-09-09 00:58:28 -06:00 |
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b7cd786182
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move some stuff
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2021-09-09 00:56:45 -06:00 |
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96295e0a7c
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update README.md
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2021-09-09 00:54:41 -06:00 |
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0fb69204e0
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indentation
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2021-09-09 00:45:36 -06:00 |
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fb3a59381b
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remove hack from when I was compiling for rv64i and running on rv32i
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2021-09-09 00:44:49 -06:00 |
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5413047464
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restore CPPFLAGS
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2021-09-09 00:32:24 -06:00 |
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a9c5f815ba
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disable non-functional test_c
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2021-09-09 00:20:20 -06:00 |
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7ab99bb5ff
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add start of JTAG TAP
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2021-09-09 00:06:57 -06:00 |
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625001152d
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update tests
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2021-09-09 00:06:15 -06:00 |
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8901e538e1
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rename basic_test to test_basic
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2021-09-08 23:44:45 -06:00 |
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d8161743eb
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add C compilation test
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2021-09-08 23:43:15 -06:00 |
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8b60773d2b
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switch to rv32i compiler
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2021-09-08 23:17:34 -06:00 |
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cb10d24050
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add README.md for basic_test
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2021-08-11 00:42:03 -06:00 |
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0caee84a0e
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add pipeline status to README.md
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2021-08-11 06:28:00 +00:00 |
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5dc815245e
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hopefully fix pipeline
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2021-08-11 00:24:05 -06:00 |
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855eb67940
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hardcode top level makefile
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2021-08-11 00:21:00 -06:00 |
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8211013a0c
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rename
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2021-08-11 00:19:50 -06:00 |
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392e0a24ed
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large restructure
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2021-08-11 00:18:46 -06:00 |
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6b0a72d516
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add a basic diagram
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2021-07-03 21:18:03 -06:00 |
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8decf52443
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make mem_data_rvalid a reg in tb
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2021-07-03 21:17:42 -06:00 |
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cc4101c1f8
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prevent simulation from printing all writes to regfile
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2021-07-03 21:02:48 -06:00 |
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34dc20f115
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fix intentional test.S error
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2021-07-03 21:01:29 -06:00 |
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c03866f56a
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BAD CODE: check pipeline's ability to detect test script failure
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2021-07-03 21:00:34 -06:00 |
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e3c52db637
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make sim will now fail if test hits fail state
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2021-07-03 20:59:03 -06:00 |
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d4ed4ec2bc
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add ability to wait for memory writes
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2021-07-03 19:39:22 -06:00 |
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