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lib/bh_assert.sv
112
lib/bh_assert.sv
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@ -1,69 +1,67 @@
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`timescale 1ns/1ps
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package bh_assert;
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int bh_assert_pass_count = 0;
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int bh_assert_fail_count = 0;
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int bh_assert_warn_count = 0;
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int bh_assert_pass_count = 0;
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int bh_assert_fail_count = 0;
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int bh_assert_warn_count = 0;
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localparam BH_ASSERT_LOG_LEVEL_FAIL = 0;
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localparam BH_ASSERT_LOG_LEVEL_ASSERT = 1;
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localparam BH_ASSERT_LOG_LEVEL_WARN = 2;
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localparam BH_ASSERT_LOG_LEVEL_INFO = 3;
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localparam BH_ASSERT_LOG_LEVEL_FAIL = 0;
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localparam BH_ASSERT_LOG_LEVEL_ASSERT = 1;
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localparam BH_ASSERT_LOG_LEVEL_WARN = 2;
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localparam BH_ASSERT_LOG_LEVEL_INFO = 3;
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logic bh_assert_log_level = BH_ASSERT_LOG_LEVEL_WARN; // 0 = errors only, 1 = all assertions, 2 = warnings, 3 = info
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logic bh_assert_log_level = BH_ASSERT_LOG_LEVEL_WARN; // 0 = errors only, 1 = all assertions, 2 = warnings, 3 = info
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localparam COLOR_RED = "\033[31m";
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localparam COLOR_YELLOW = "\033[33m";
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localparam COLOR_GREEN = "\033[32m";
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localparam COLOR_NORMAL = "\033[0;39m";
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localparam COLOR_RED = "\033[31m";
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localparam COLOR_YELLOW = "\033[33m";
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localparam COLOR_GREEN = "\033[32m";
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localparam COLOR_NORMAL = "\033[0;39m";
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task bh_assert_equal(int val, int expected, string description);
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// display results
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$timeformat(-9, 2, " ns", 20);
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$display(
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"%t: %s: %d %s %d - %s",
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$time,
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val == expected ? {COLOR_GREEN, "PASS", COLOR_NORMAL} : {COLOR_RED, "FAIL", COLOR_NORMAL},
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val,
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val == expected ? "==" : "!=",
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expected,
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description
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);
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task bh_assert_equal(int val, int expected, string description);
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// display results
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$timeformat(-9, 2, " ns", 20);
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$display(
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"%t: %s: %d %s %d - %s",
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$time,
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val == expected ? {COLOR_GREEN, "PASS", COLOR_NORMAL} : {COLOR_RED, "FAIL", COLOR_NORMAL},
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val,
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val == expected ? "==" : "!=",
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expected,
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description
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);
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// update statistics
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if (val == expected) begin
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bh_assert_pass_count = bh_assert_pass_count + 1;
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end else begin
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bh_assert_fail_count = bh_assert_fail_count + 1;
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end
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endtask
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// update statistics
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if (val == expected) begin
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bh_assert_pass_count = bh_assert_pass_count + 1;
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end else begin
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bh_assert_fail_count = bh_assert_fail_count + 1;
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end
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endtask
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task bh_assert_stats;
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$timeformat(-9, 2, " ns", 20);
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$display("%t: DONE: %1d pass, %1d fail, %1d warn", $time, bh_assert_pass_count, bh_assert_fail_count, bh_assert_warn_count);
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if (bh_assert_pass_count + bh_assert_fail_count == 0) begin
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$display("%sERROR%s: no assertions found", COLOR_YELLOW, COLOR_NORMAL);
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// TODO: error in a better way?
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end else if (bh_assert_fail_count > 0) begin
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$display("%sERROR%s: some tests failed", COLOR_RED, COLOR_NORMAL);
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end else begin
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$display("%sSUCCESS%s: all tests passed", COLOR_GREEN, COLOR_NORMAL);
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end
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endtask
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task bh_assert_stats;
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$timeformat(-9, 2, " ns", 20);
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$display("%t: DONE: %1d pass, %1d fail, %1d warn", $time, bh_assert_pass_count, bh_assert_fail_count, bh_assert_warn_count);
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if (bh_assert_pass_count + bh_assert_fail_count == 0) begin
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$display("%sERROR%s: no assertions found", COLOR_YELLOW, COLOR_NORMAL);
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// TODO: error in a better way?
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end else if (bh_assert_fail_count > 0) begin
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$display("%sERROR%s: some tests failed", COLOR_RED, COLOR_NORMAL);
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end else begin
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$display("%sSUCCESS%s: all tests passed", COLOR_GREEN, COLOR_NORMAL);
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end
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endtask
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task bh_info(string description);
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if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_INFO) begin
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$display("%t: INFO: %s", $time, description);
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end
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endtask
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task bh_info(string description);
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if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_INFO) begin
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$display("%t: INFO: %s", $time, description);
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end
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endtask
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task bh_warn(string description);
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if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_WARN) begin
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$display("%t: %sWARN%s: %s", $time, COLOR_YELLOW, COLOR_NORMAL, description);
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end
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bh_assert_warn_count = bh_assert_warn_count + 1;
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endtask
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task bh_warn(string description);
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if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_WARN) begin
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$display("%t: %sWARN%s: %s", $time, COLOR_YELLOW, COLOR_NORMAL, description);
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end
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bh_assert_warn_count = bh_assert_warn_count + 1;
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endtask
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endpackage
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endpackage
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@ -12,43 +12,42 @@ module skidbuffer #(
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output logic out_valid,
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input logic out_ready
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);
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logic buffer_filled = 0;
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logic [WIDTH-1:0] buffer_val;
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logic buffer_filled = 0;
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logic [WIDTH-1:0] buffer_val;
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always_ff @(posedge clk) begin
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if (reset) begin
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buffer_filled <= 0;
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end else begin
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if (in_valid && in_ready) begin
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// input always gets stored whether it needs to be or not
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buffer_val <= in;
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end
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if (buffer_filled) begin
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if ((out_valid && out_ready) && !(in_valid && in_ready)) begin
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// out_valid = 1 since buffer is full
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buffer_filled <= 0;
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end
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always_ff @(posedge clk) begin
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if (reset) begin
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buffer_filled <= 0;
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end else begin
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if ((in_valid && in_ready) && !(out_valid && out_ready)) begin
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// in_ready = 1 since buffer is empty
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buffer_filled <= 1;
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if (in_valid && in_ready) begin
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// input always gets stored whether it needs to be or not
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buffer_val <= in;
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end
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if (buffer_filled) begin
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if ((out_valid && out_ready) && !(in_valid && in_ready)) begin
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// out_valid = 1 since buffer is full
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buffer_filled <= 0;
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end
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end else begin
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if ((in_valid && in_ready) && !(out_valid && out_ready)) begin
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// in_ready = 1 since buffer is empty
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buffer_filled <= 1;
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end
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end
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end
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end
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end
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always_comb begin
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if (buffer_filled) begin
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in_ready = out_ready;
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out_valid = 1;
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out = buffer_val;
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end else begin
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in_ready = 1;
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out_valid = in_valid;
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out = in;
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always_comb begin
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if (buffer_filled) begin
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in_ready = out_ready;
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out_valid = 1;
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out = buffer_val;
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end else begin
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in_ready = 1;
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out_valid = in_valid;
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out = in;
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end
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end
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end
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endmodule
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@ -5,79 +5,77 @@ import bh_assert::bh_assert_equal;
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import bh_assert::bh_assert_stats;
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module skidbuffer_tb();
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parameter WIDTH = 15;
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parameter TEST_LIST_LENGTH = 256;
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parameter WIDTH = 15;
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parameter TEST_LIST_LENGTH = 256;
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logic clk = 0;
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logic reset = 1;
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logic [WIDTH-1:0] in;
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logic in_valid = 0;
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wire in_ready;
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wire [WIDTH-1:0] out;
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wire out_valid;
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logic out_ready = 0;
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logic clk = 0;
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logic reset = 1;
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logic [WIDTH-1:0] in;
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logic in_valid = 0;
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wire in_ready;
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wire [WIDTH-1:0] out;
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wire out_valid;
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logic out_ready = 0;
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skidbuffer #(
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.WIDTH(WIDTH)
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) dut (
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.clk(clk),
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.reset(reset),
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.in(in),
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.in_valid(in_valid),
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.in_ready(in_ready),
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.out(out),
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.out_valid(out_valid),
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.out_ready(out_ready)
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);
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skidbuffer #(
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.WIDTH(WIDTH)
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) dut (
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.clk(clk),
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.reset(reset),
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.in(in),
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.in_valid(in_valid),
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.in_ready(in_ready),
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.out(out),
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.out_valid(out_valid),
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.out_ready(out_ready)
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);
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integer i = 0;
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integer in_count = 0;
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integer out_count = 0;
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logic [WIDTH-1:0] in_list [0:TEST_LIST_LENGTH-1];
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integer i = 0;
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integer in_count = 0;
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integer out_count = 0;
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logic [WIDTH-1:0] in_list [0:TEST_LIST_LENGTH-1];
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assign in = in_list[in_count];
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assign in = in_list[in_count];
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always #5 clk = !clk;
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always #5 clk = !clk;
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initial begin
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$dumpfile("skidbuffer_tb.vcd");
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$dumpvars(0, skidbuffer_tb);
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initial begin
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$dumpfile("skidbuffer_tb.vcd");
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$dumpvars(0, skidbuffer_tb);
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for (i=0; i<TEST_LIST_LENGTH; i=i+1) begin
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in_list[i] = $urandom();
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end
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for (i=0; i<TEST_LIST_LENGTH; i=i+1) begin
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in_list[i] = $urandom();
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end
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#10
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reset = 0;
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while (out_count < TEST_LIST_LENGTH) begin
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#10
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if (!in_valid || (in_valid && in_ready)) begin
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in_valid = $urandom_range(1);
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reset = 0;
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while (out_count < TEST_LIST_LENGTH) begin
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#10
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if (!in_valid || (in_valid && in_ready)) begin
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in_valid = $urandom_range(1);
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end
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if (!out_ready || (out_ready && out_valid)) begin
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out_ready = $urandom_range(1);
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end
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end
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if (!out_ready || (out_ready && out_valid)) begin
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out_ready = $urandom_range(1);
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bh_assert_stats();
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$finish;
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end
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always @(posedge clk) begin
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if (reset == 0 && in_valid && in_ready) begin
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in_count <= in_count + 1;
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end
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if (reset == 0 && out_valid && out_ready) begin
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bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
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out_count <= out_count + 1;
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end
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end
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bh_assert_stats();
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$finish;
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end
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wire [WIDTH-1:0] out_correct;
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assign out_correct = in_list[out_count];
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always @(posedge clk) begin
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if (reset == 0 && in_valid && in_ready) begin
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in_count <= in_count + 1;
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end
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if (reset == 0 && out_valid && out_ready) begin
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bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
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out_count <= out_count + 1;
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end
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end
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wire [WIDTH-1:0] out_correct;
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assign out_correct = in_list[out_count];
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endmodule
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endmodule
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