brendanhaines/cpu
1
0
Fork 0
mirror of https://gitlab.com/brendanhaines/cpu.git synced 2024-12-25 10:36:49 -07:00
Code Issues Packages Projects Releases Wiki Activity

indentation

Browse Source
This commit is contained in:
Brendan Haines 2021-09-09 00:45:36 -06:00
parent fb3a59381b
commit 0fb69204e0
1 changed files with 68 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

136
src/bh_cpu.v
View File

@ -475,79 +475,79 @@ always @(posedge clk) begin: pipeline_update
end
end else begin
// IF
if (!s_if_stall) begin
r_if_pc <= s_if_next_pc;
end
// IF
if (!s_if_stall) begin
r_if_pc <= s_if_next_pc;
end
// ID
if (!s_id_stall) begin
r_id_pc <= r_if_pc;
r_id_inst <= s_if_inst;
r_id_valid <= ~(s_ex_take_branch && r_ex_valid);
end
// ID
if (!s_id_stall) begin
r_id_pc <= r_if_pc;
r_id_inst <= s_if_inst;
r_id_valid <= ~(s_ex_take_branch && r_ex_valid);
end
// EX
if (!s_ex_stall) begin
r_ex_pc <= r_id_pc;
r_ex_inst <= r_id_inst;
r_ex_rs1 <= s_id_rs1;
r_ex_rs2 <= s_id_rs2;
r_ex_rd <= s_id_rd;
r_ex_s1 <= s_id_s1;
r_ex_s2 <= s_id_s2;
r_ex_aluop <= s_id_aluop;
r_ex_jump <= s_id_jump;
r_ex_branch <= s_id_branch;
r_ex_store <= s_id_store;
r_ex_load <= s_id_load;
r_ex_valid <= r_id_valid && ~(s_ex_take_branch && r_ex_valid) && ~(s_id_stall && r_id_valid);
r_ex_branch_pol <= s_id_branch_pol;
r_ex_immed_btype <= s_id_immed_btype;
end
// EX
if (!s_ex_stall) begin
r_ex_pc <= r_id_pc;
r_ex_inst <= r_id_inst;
r_ex_rs1 <= s_id_rs1;
r_ex_rs2 <= s_id_rs2;
r_ex_rd <= s_id_rd;
r_ex_s1 <= s_id_s1;
r_ex_s2 <= s_id_s2;
r_ex_aluop <= s_id_aluop;
r_ex_jump <= s_id_jump;
r_ex_branch <= s_id_branch;
r_ex_store <= s_id_store;
r_ex_load <= s_id_load;
r_ex_valid <= r_id_valid && ~(s_ex_take_branch && r_ex_valid) && ~(s_id_stall && r_id_valid);
r_ex_branch_pol <= s_id_branch_pol;
r_ex_immed_btype <= s_id_immed_btype;
end
// MEM
if (!s_mem_stall) begin
r_mem_pc <= r_ex_pc;
r_mem_inst <= r_ex_inst;
r_mem_rs1 <= r_ex_rs1;
r_mem_rs2 <= r_ex_rs2;
r_mem_rd <= r_ex_rd;
r_mem_s1 <= r_ex_s1;
r_mem_s2 <= r_ex_s2;
r_mem_alu_out <= s_ex_alu_out;
r_mem_alu_zero <= s_ex_alu_zero;
r_mem_store <= r_ex_store;
r_mem_load <= r_ex_load;
r_mem_valid <= r_ex_valid;
r_mem_branch <= r_ex_branch;
r_mem_ra <= s_ex_ra;
r_mem_jump <= r_ex_jump;
end
// MEM
if (!s_mem_stall) begin
r_mem_pc <= r_ex_pc;
r_mem_inst <= r_ex_inst;
r_mem_rs1 <= r_ex_rs1;
r_mem_rs2 <= r_ex_rs2;
r_mem_rd <= r_ex_rd;
r_mem_s1 <= r_ex_s1;
r_mem_s2 <= r_ex_s2;
r_mem_alu_out <= s_ex_alu_out;
r_mem_alu_zero <= s_ex_alu_zero;
r_mem_store <= r_ex_store;
r_mem_load <= r_ex_load;
r_mem_valid <= r_ex_valid;
r_mem_branch <= r_ex_branch;
r_mem_ra <= s_ex_ra;
r_mem_jump <= r_ex_jump;
end
// WB
if (1) begin
r_wb_pc <= r_mem_pc;
r_wb_inst <= r_mem_inst;
r_wb_rs1 <= r_mem_rs1;
r_wb_rs2 <= r_mem_rs2;
r_wb_rd <= r_mem_rd;
r_wb_alu_out <= r_mem_alu_out;
r_wb_valid <= r_mem_valid;
r_wb_branch <= r_mem_branch;
r_wb_ra <= r_mem_ra;
r_wb_jump <= r_mem_jump;
r_wb_load <= r_mem_load;
r_wb_load_data <= s_mem_load_data;
end
// WB
if (1) begin
r_wb_pc <= r_mem_pc;
r_wb_inst <= r_mem_inst;
r_wb_rs1 <= r_mem_rs1;
r_wb_rs2 <= r_mem_rs2;
r_wb_rd <= r_mem_rd;
r_wb_alu_out <= r_mem_alu_out;
r_wb_valid <= r_mem_valid;
r_wb_branch <= r_mem_branch;
r_wb_ra <= r_mem_ra;
r_wb_jump <= r_mem_jump;
r_wb_load <= r_mem_load;
r_wb_load_data <= s_mem_load_data;
end
// Register File
// TODO: should I write if s_wb_stall=1?
if (r_wb_rd != 0 && s_wb_write && r_wb_valid) begin
regfile[r_wb_rd] <= s_wb_data;
// $display("%0t:\tPC=0x%h\tx%02d=0x%h", $time, r_id_pc, r_wb_rd, s_wb_data);
end
// Register File
// TODO: should I write if s_wb_stall=1?
if (r_wb_rd != 0 && s_wb_write && r_wb_valid) begin
regfile[r_wb_rd] <= s_wb_data;
// $display("%0t:\tPC=0x%h\tx%02d=0x%h", $time, r_id_pc, r_wb_rd, s_wb_data);
end
end
end