restructure testbenches and common code

This commit is contained in:
Brendan Haines 2022-12-01 00:45:57 -07:00
parent a2b0b2a709
commit ebc3b22ac7
7 changed files with 184 additions and 8 deletions

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@ -1,3 +1,6 @@
`timescale 1ns/1ps
package bh_assert;
int bh_assert_pass_count = 0;
int bh_assert_fail_count = 0;
@ -46,3 +49,4 @@ function void bh_info(string description);
end
endfunction
endpackage

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@ -26,14 +26,13 @@ always_ff @(posedge clk) begin
end
if (buffer_filled) begin
if (out_ready && !(in_valid && in_ready)) begin
if ((out_valid && out_ready) && !(in_valid && in_ready)) begin
// out_valid = 1 since buffer is full
buffer_filled <= 0;
end
end else begin
if (in_valid && !(out_valid && out_ready)) begin
if ((in_valid && in_ready) && !(out_valid && out_ready)) begin
// in_ready = 1 since buffer is empty
buffer_val = in;
buffer_filled <= 1;
end
end

3
lib/tb/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
*.log
*.gtkw
*.vcd

23
lib/tb/Makefile Normal file
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@ -0,0 +1,23 @@
all: verify
TESTBENCH_V = $(wildcard *_tb.sv)
SOURCE_V = $(wildcard ../*.v ../*.sv)
LOGS = $(TESTBENCH_V:.sv=.log)
# Hardware compilation
%.out: %.sv $(SOURCE_V)
iverilog -g2012 -o $@ $^
# Run test
%.vcd %.log: %.out
./$< | tee $(patsubst %.out, %.log, $<)
verify: $(LOGS)
@! grep -q "ERROR" $^
@grep -q "SUCCESS" $^
clean:
rm -rf *.vcd *.log *.out
.SECONDARY: %.log %.vcd
.PHONY: all clean verify

147
lib/tb/skidbuffer_tb.sv Normal file
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@ -0,0 +1,147 @@
`timescale 1ns/1ps
// import bh_assert::*;
module skidbuffer_tb();
int bh_assert_pass_count = 0;
int bh_assert_fail_count = 0;
int bh_assert_warn_count = 0;
localparam BH_ASSERT_LOG_LEVEL_FAIL = 0;
localparam BH_ASSERT_LOG_LEVEL_ASSERT = 1;
localparam BH_ASSERT_LOG_LEVEL_WARN = 2;
localparam BH_ASSERT_LOG_LEVEL_INFO = 3;
logic bh_assert_log_level = BH_ASSERT_LOG_LEVEL_WARN; // 0 = errors only, 1 = all assertions, 2 = warnings, 3 = info
localparam COLOR_RED = "\033[31m";
localparam COLOR_YELLOW = "\033[33m";
localparam COLOR_GREEN = "\033[32m";
localparam COLOR_NORMAL = "\033[0;39m";
task bh_assert_equal(int val, int expected, string description);
// display results
$timeformat(-9, 2, " ns", 20);
$display(
"%t: %s: %d %s %d - %s",
$time,
val == expected ? {COLOR_GREEN, "PASS", COLOR_NORMAL} : {COLOR_RED, "FAIL", COLOR_NORMAL},
val,
val == expected ? "==" : "!=",
expected,
description
);
// update statistics
if (val == expected) begin
bh_assert_pass_count = bh_assert_pass_count + 1;
end else begin
bh_assert_fail_count = bh_assert_fail_count + 1;
end
endtask
task bh_assert_stats;
$timeformat(-9, 2, " ns", 20);
$display("%t: DONE: %1d pass, %1d fail, %1d warn", $time, bh_assert_pass_count, bh_assert_fail_count, bh_assert_warn_count);
if (bh_assert_pass_count + bh_assert_fail_count == 0) begin
$display("%sERROR%s: no assertions found", COLOR_YELLOW, COLOR_NORMAL);
// TODO: error in a better way?
end else if (bh_assert_fail_count > 0) begin
$display("%sERROR%s: some tests failed", COLOR_RED, COLOR_NORMAL);
end else begin
$display("%sSUCCESS%s: all tests passed", COLOR_GREEN, COLOR_NORMAL);
end
endtask
task bh_info(string description);
if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_INFO) begin
$display("%t: INFO: %s", $time, description);
end
endtask
task bh_warn(string description);
if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_WARN) begin
$display("%t: %sWARN%s: %s", $time, COLOR_YELLOW, COLOR_NORMAL, description);
end
bh_assert_warn_count = bh_assert_warn_count + 1;
endtask
parameter WIDTH = 15;
parameter TEST_LIST_LENGTH = 256;
logic clk = 0;
logic reset = 1;
logic [WIDTH-1:0] in;
logic in_valid = 0;
wire in_ready;
wire [WIDTH-1:0] out;
wire out_valid;
logic out_ready = 0;
skidbuffer #(
.WIDTH(WIDTH)
) dut (
.clk(clk),
.reset(reset),
.in(in),
.in_valid(in_valid),
.in_ready(in_ready),
.out(out),
.out_valid(out_valid),
.out_ready(out_ready)
);
integer i = 0;
integer in_count = 0;
integer out_count = 0;
logic [WIDTH-1:0] in_list [0:TEST_LIST_LENGTH-1];
assign in = in_list[in_count];
always #5 clk = !clk;
initial begin
$dumpfile("skidbuffer_tb.vcd");
$dumpvars(0, skidbuffer_tb);
for (i=0; i<TEST_LIST_LENGTH; i=i+1) begin
in_list[i] = $urandom();
end
#10
reset = 0;
while (out_count < TEST_LIST_LENGTH) begin
#10
if (!in_valid || (in_valid && in_ready)) begin
in_valid = $urandom_range(1);
end
if (!out_ready || (out_ready && out_valid)) begin
out_ready = $urandom_range(1);
end
end
bh_assert_stats();
$finish;
end
always @(posedge clk) begin
if (reset == 0 && in_valid && in_ready) begin
in_count <= in_count + 1;
end
if (reset == 0 && out_valid && out_ready) begin
bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
bh_warn("hello warning");
bh_info("hello info");
out_count <= out_count + 1;
end
end
wire [WIDTH-1:0] out_correct;
assign out_correct = in_list[out_count];
endmodule

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@ -111,6 +111,7 @@ always_ff @(posedge clk) begin
((axil_wvalid && axil_wready) || wdata_valid) &&
((axil_awvalid && axil_awready) || waddr_valid) &&
!w_complete
// TODO: check for wdata_legal (and combinatorial wdata_legal)
) begin
if (state_wb == STATE_IDLE) begin
state_wb <= STATE_WRITE;

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@ -2,7 +2,8 @@ all: verify
TESTBENCH_V = $(wildcard *tb.sv)
SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
SOURCE_V += $(wildcard ../common/*.v) $(wildcard ../common/*.sv)
SOURCE_V += $(wildcard ../../lib/*.v ../../lib/*.sv)
SOURCE_V += $(wildcard ../common/*.v ../common/*.sv)
LOGS = $(TESTBENCH_V:.sv=.log)
SOURCE_C = $(wildcard *.c)
@ -51,10 +52,8 @@ LDFLAGS = -melf32lriscv_ilp32
./$< | tee $(patsubst %.out, %.log, $<)
verify: $(LOGS)
@echo "Checking log for \"ERROR:\"..."
@! grep "ERROR:" $^
@echo "Checking log for \"SUCCESS:\"..."
@grep "SUCCESS:" $^
@! grep -q "ERROR" $^
@grep -q "SUCCESS" $^
clean:
rm -rf *.vcd *.log *.out *.hex