mirror of
https://gitlab.com/brendanhaines/cpu.git
synced 2024-12-25 10:36:49 -07:00
update README.md
This commit is contained in:
parent
0fb69204e0
commit
96295e0a7c
11
README.md
11
README.md
|
@ -2,13 +2,18 @@
|
|||
|
||||
# RISC-V CPU
|
||||
|
||||
Harvard architecture
|
||||
Short Term To Do:
|
||||
* add stalls for memory access
|
||||
* use AXI for memory access
|
||||
* add tests for non-pipelined case
|
||||
* get C working (may depend on memory stalls)
|
||||
|
||||
Desired features:
|
||||
* 1- or 5-stage pipeline selectable via parameter
|
||||
* AXI-lite Master for both instruction and data memory
|
||||
* 32, 64, or 128 bit word size
|
||||
* floating point support
|
||||
* 32, 64, (or 128?) bit word size
|
||||
* floating point
|
||||
* multiplication
|
||||
* division
|
||||
* instruction and data caches
|
||||
* JTAG debug probe
|
||||
|
|
Loading…
Reference in New Issue
Block a user