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RISC-V CPU
81 Commits 2 Branches 0 Tags 172 KiB
Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
Shell 0.4%
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Brendan Haines d8161743eb add C compilation test
2021-09-08 23:43:15 -06:00
documentation add a basic diagram 2021-07-03 21:18:03 -06:00
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testbench add C compilation test 2021-09-08 23:43:15 -06:00
.gitignore switch to rv32i compiler 2021-09-08 23:17:34 -06:00
.gitlab-ci.yml hopefully fix pipeline 2021-08-11 00:24:05 -06:00
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README.md add pipeline status to README.md 2021-08-11 06:28:00 +00:00

README.md

pipeline status

RISC-V CPU

Harvard architecture

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, or 128 bit word size
  • floating point support
  • multiplication
  • division
  • instruction and data caches