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RISC-V CPU
93 Commits 2 Branches 0 Tags 172 KiB
Verilog 44.4%
SystemVerilog 36.4%
Assembly 14.9%
Makefile 3.8%
Shell 0.4%
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README.md

pipeline status

RISC-V CPU

Short Term To Do:

  • add stalls for memory access
  • use AXI for memory access (depends on AXIL memory module for test)
  • add tests for non-pipelined case
  • get C working (may depend on memory stalls)

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, (or 128?) bit word size
  • floating point
  • multiplication
  • division
  • instruction and data caches
  • JTAG debug probe