RISC-V CPU
Go to file
2022-01-27 21:47:20 -07:00
docs move some stuff 2021-09-09 00:56:45 -06:00
other_projects add start of JTAG TAP 2021-09-09 00:06:57 -06:00
src indentation 2021-09-09 00:45:36 -06:00
tests rename testbench to tests 2021-09-09 00:58:28 -06:00
.gitignore switch to rv32i compiler 2021-09-08 23:17:34 -06:00
.gitlab-ci.yml update .gitlab-ci.yml 2022-01-27 21:47:20 -07:00
README.md move some stuff 2021-09-09 00:56:45 -06:00

pipeline status

RISC-V CPU

Short Term To Do:

  • add stalls for memory access
  • use AXI for memory access (depends on AXIL memory module for test)
  • add tests for non-pipelined case
  • get C working (may depend on memory stalls)

Desired features:

  • 1- or 5-stage pipeline selectable via parameter
  • AXI-lite Master for both instruction and data memory
  • 32, 64, (or 128?) bit word size
  • floating point
  • multiplication
  • division
  • instruction and data caches
  • JTAG debug probe