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move axil bridge

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This commit is contained in:
Brendan Haines 2022-12-01 01:13:23 -07:00
parent 5d3d9b222f
commit e301d2c4d2
3 changed files with 13 additions and 3 deletions
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2
tests/common/axi4_lite.sv → lib/axil_wb_bridge.sv
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@ -1,6 +1,6 @@
// TODO: improve throughput. Currently limited to 1 write every 3 cycles and read every 2 cycles (plus wb slave latency)
module axi4l_wb_bridge #(
module axil_wb_bridge #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32
)(

13
tests/common/axi4_lite_tb.sv → lib/tb/axil_wb_bridge_tb.sv
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@ -1,4 +1,10 @@
module axi4_lite_tb();
`include "bh_assert.sv"
`timescale 1ns/1ps
import bh_assert::bh_assert_equal;
import bh_assert::bh_assert_stats;
module axil_wb_bridge_tb();
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 32;
@ -39,7 +45,7 @@ logic wb_stb_o;
logic wb_ack_i;
logic wb_cyc_o;
axi4l_wb_bridge #(
axil_wb_bridge #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) dut(
@ -91,6 +97,9 @@ always #5 clk <= !clk;
initial begin
#10
bh_assert_stats();
$finish;
end
endmodule

1
lib/tb/skidbuffer_tb.sv
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@ -60,6 +60,7 @@ module skidbuffer_tb();
end
end
#10
bh_assert_stats();
$finish;
end