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449efd3c3c
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use systemverilog 2012 for simulation
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2022-11-19 18:41:25 -07:00 |
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8055444b99
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add correct riscv toolchain. Build takes forever so I'll probably add the binaries later
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2022-11-19 18:40:37 -07:00 |
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c1ec8520be
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implement axi-lite to wishbone bridge. Untested
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2022-11-19 18:37:35 -07:00 |
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03828419a9
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add linting in vscode
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2022-11-19 16:27:52 -07:00 |
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0fea83e14c
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update .gitlab-ci.yml
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2022-01-27 21:47:20 -07:00 |
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12e3078c2a
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should fix CI after moving tests
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2021-09-09 01:06:19 -06:00 |
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2d69722cb1
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rename testbench to tests
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2021-09-09 00:58:28 -06:00 |
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b7cd786182
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move some stuff
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2021-09-09 00:56:45 -06:00 |
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96295e0a7c
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update README.md
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2021-09-09 00:54:41 -06:00 |
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0fb69204e0
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indentation
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2021-09-09 00:45:36 -06:00 |
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fb3a59381b
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remove hack from when I was compiling for rv64i and running on rv32i
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2021-09-09 00:44:49 -06:00 |
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5413047464
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restore CPPFLAGS
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2021-09-09 00:32:24 -06:00 |
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a9c5f815ba
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disable non-functional test_c
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2021-09-09 00:20:20 -06:00 |
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7ab99bb5ff
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add start of JTAG TAP
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2021-09-09 00:06:57 -06:00 |
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625001152d
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update tests
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2021-09-09 00:06:15 -06:00 |
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8901e538e1
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rename basic_test to test_basic
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2021-09-08 23:44:45 -06:00 |
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d8161743eb
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add C compilation test
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2021-09-08 23:43:15 -06:00 |
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8b60773d2b
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switch to rv32i compiler
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2021-09-08 23:17:34 -06:00 |
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cb10d24050
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add README.md for basic_test
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2021-08-11 00:42:03 -06:00 |
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0caee84a0e
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add pipeline status to README.md
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2021-08-11 06:28:00 +00:00 |
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5dc815245e
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hopefully fix pipeline
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2021-08-11 00:24:05 -06:00 |
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855eb67940
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hardcode top level makefile
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2021-08-11 00:21:00 -06:00 |
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8211013a0c
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rename
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2021-08-11 00:19:50 -06:00 |
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392e0a24ed
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large restructure
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2021-08-11 00:18:46 -06:00 |
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6b0a72d516
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add a basic diagram
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2021-07-03 21:18:03 -06:00 |
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8decf52443
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make mem_data_rvalid a reg in tb
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2021-07-03 21:17:42 -06:00 |
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cc4101c1f8
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prevent simulation from printing all writes to regfile
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2021-07-03 21:02:48 -06:00 |
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34dc20f115
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fix intentional test.S error
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2021-07-03 21:01:29 -06:00 |
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c03866f56a
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BAD CODE: check pipeline's ability to detect test script failure
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2021-07-03 21:00:34 -06:00 |
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e3c52db637
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make sim will now fail if test hits fail state
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2021-07-03 20:59:03 -06:00 |
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d4ed4ec2bc
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add ability to wait for memory writes
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2021-07-03 19:39:22 -06:00 |
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dd8bad9610
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Fix .gitlab-ci.yml file
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2021-07-04 00:52:26 +00:00 |
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bd6c60fe92
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Fix .gitlab-ci.yml
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2021-07-04 00:50:25 +00:00 |
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9707698281
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cleanup
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2021-07-03 18:48:07 -06:00 |
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2225ccd311
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trying to also use .c files. Not yet working but doesn't break .as files
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2021-07-02 05:16:30 -06:00 |
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b79c572a22
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tweak makefile
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2021-07-02 04:58:58 -06:00 |
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c0852697df
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remove outdated comment
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2021-07-02 04:52:48 -06:00 |
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5e87ea0c75
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fix loading of sectios other than .text and get rid of massive sed chain for .hex generation
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2021-07-02 04:47:40 -06:00 |
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9031b5b4c5
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working load/store word with byte addressed memory
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2021-07-02 04:32:25 -06:00 |
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35423ce4af
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works with 8bit addressed memory (rather than word addressed)
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2021-07-02 04:22:33 -06:00 |
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57e745b336
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more clean up and reorganization from memory restructuring
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2021-07-02 03:28:21 -06:00 |
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69e4ea9204
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clean up core_tb.v a little
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2021-07-02 03:20:38 -06:00 |
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07d317eb6e
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add trailing NOP instructions so non-initialized memory doesn't cause issues
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2021-07-02 03:14:37 -06:00 |
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9ff977c1be
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partially working with common address space. loading of .data section has been disabled
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2021-07-02 03:11:50 -06:00 |
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17a95b58c8
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fix the code issues I just introduced
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2021-07-02 02:39:43 -06:00 |
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0a9b182ef7
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BAD CODE: testing that CI pipeline catches verilog issues
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2021-07-02 02:39:13 -06:00 |
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07c2fb570c
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BAD CODE: to test CI pipeline
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2021-07-02 02:38:01 -06:00 |
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e24d230f1a
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Update .gitlab-ci.yml file
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2021-07-02 08:35:22 +00:00 |
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efe2696313
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Update .gitlab-ci.yml file
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2021-07-02 08:33:53 +00:00 |
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04443b191a
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Update .gitlab-ci.yml file
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2021-07-02 08:33:02 +00:00 |
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