Commit Graph

97 Commits

Author SHA1 Message Date
449efd3c3c use systemverilog 2012 for simulation 2022-11-19 18:41:25 -07:00
8055444b99 add correct riscv toolchain. Build takes forever so I'll probably add the binaries later 2022-11-19 18:40:37 -07:00
c1ec8520be implement axi-lite to wishbone bridge. Untested 2022-11-19 18:37:35 -07:00
03828419a9 add linting in vscode 2022-11-19 16:27:52 -07:00
0fea83e14c update .gitlab-ci.yml 2022-01-27 21:47:20 -07:00
12e3078c2a should fix CI after moving tests 2021-09-09 01:06:19 -06:00
2d69722cb1 rename testbench to tests 2021-09-09 00:58:28 -06:00
b7cd786182 move some stuff 2021-09-09 00:56:45 -06:00
96295e0a7c update README.md 2021-09-09 00:54:41 -06:00
0fb69204e0 indentation 2021-09-09 00:45:36 -06:00
fb3a59381b remove hack from when I was compiling for rv64i and running on rv32i 2021-09-09 00:44:49 -06:00
5413047464 restore CPPFLAGS 2021-09-09 00:32:24 -06:00
a9c5f815ba disable non-functional test_c 2021-09-09 00:20:20 -06:00
7ab99bb5ff add start of JTAG TAP 2021-09-09 00:06:57 -06:00
625001152d update tests 2021-09-09 00:06:15 -06:00
8901e538e1 rename basic_test to test_basic 2021-09-08 23:44:45 -06:00
d8161743eb add C compilation test 2021-09-08 23:43:15 -06:00
8b60773d2b switch to rv32i compiler 2021-09-08 23:17:34 -06:00
cb10d24050 add README.md for basic_test 2021-08-11 00:42:03 -06:00
0caee84a0e add pipeline status to README.md 2021-08-11 06:28:00 +00:00
5dc815245e hopefully fix pipeline 2021-08-11 00:24:05 -06:00
855eb67940 hardcode top level makefile 2021-08-11 00:21:00 -06:00
8211013a0c rename 2021-08-11 00:19:50 -06:00
392e0a24ed large restructure 2021-08-11 00:18:46 -06:00
6b0a72d516 add a basic diagram 2021-07-03 21:18:03 -06:00
8decf52443 make mem_data_rvalid a reg in tb 2021-07-03 21:17:42 -06:00
cc4101c1f8 prevent simulation from printing all writes to regfile 2021-07-03 21:02:48 -06:00
34dc20f115 fix intentional test.S error 2021-07-03 21:01:29 -06:00
c03866f56a BAD CODE: check pipeline's ability to detect test script failure 2021-07-03 21:00:34 -06:00
e3c52db637 make sim will now fail if test hits fail state 2021-07-03 20:59:03 -06:00
d4ed4ec2bc add ability to wait for memory writes 2021-07-03 19:39:22 -06:00
dd8bad9610 Fix .gitlab-ci.yml file 2021-07-04 00:52:26 +00:00
bd6c60fe92 Fix .gitlab-ci.yml 2021-07-04 00:50:25 +00:00
9707698281 cleanup 2021-07-03 18:48:07 -06:00
2225ccd311 trying to also use .c files. Not yet working but doesn't break .as files 2021-07-02 05:16:30 -06:00
b79c572a22 tweak makefile 2021-07-02 04:58:58 -06:00
c0852697df remove outdated comment 2021-07-02 04:52:48 -06:00
5e87ea0c75 fix loading of sectios other than .text and get rid of massive sed chain for .hex generation 2021-07-02 04:47:40 -06:00
9031b5b4c5 working load/store word with byte addressed memory 2021-07-02 04:32:25 -06:00
35423ce4af works with 8bit addressed memory (rather than word addressed) 2021-07-02 04:22:33 -06:00
57e745b336 more clean up and reorganization from memory restructuring 2021-07-02 03:28:21 -06:00
69e4ea9204 clean up core_tb.v a little 2021-07-02 03:20:38 -06:00
07d317eb6e add trailing NOP instructions so non-initialized memory doesn't cause issues 2021-07-02 03:14:37 -06:00
9ff977c1be partially working with common address space. loading of .data section has been disabled 2021-07-02 03:11:50 -06:00
17a95b58c8 fix the code issues I just introduced 2021-07-02 02:39:43 -06:00
0a9b182ef7 BAD CODE: testing that CI pipeline catches verilog issues 2021-07-02 02:39:13 -06:00
07c2fb570c BAD CODE: to test CI pipeline 2021-07-02 02:38:01 -06:00
e24d230f1a Update .gitlab-ci.yml file 2021-07-02 08:35:22 +00:00
efe2696313 Update .gitlab-ci.yml file 2021-07-02 08:33:53 +00:00
04443b191a Update .gitlab-ci.yml file 2021-07-02 08:33:02 +00:00