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cc4101c1f8
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prevent simulation from printing all writes to regfile
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2021-07-03 21:02:48 -06:00 |
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e3c52db637
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make sim will now fail if test hits fail state
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2021-07-03 20:59:03 -06:00 |
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d4ed4ec2bc
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add ability to wait for memory writes
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2021-07-03 19:39:22 -06:00 |
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5e87ea0c75
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fix loading of sectios other than .text and get rid of massive sed chain for .hex generation
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2021-07-02 04:47:40 -06:00 |
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9031b5b4c5
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working load/store word with byte addressed memory
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2021-07-02 04:32:25 -06:00 |
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35423ce4af
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works with 8bit addressed memory (rather than word addressed)
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2021-07-02 04:22:33 -06:00 |
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57e745b336
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more clean up and reorganization from memory restructuring
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2021-07-02 03:28:21 -06:00 |
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69e4ea9204
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clean up core_tb.v a little
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2021-07-02 03:20:38 -06:00 |
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07d317eb6e
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add trailing NOP instructions so non-initialized memory doesn't cause issues
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2021-07-02 03:14:37 -06:00 |
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9ff977c1be
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partially working with common address space. loading of .data section has been disabled
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2021-07-02 03:11:50 -06:00 |
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17a95b58c8
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fix the code issues I just introduced
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2021-07-02 02:39:43 -06:00 |
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0a9b182ef7
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BAD CODE: testing that CI pipeline catches verilog issues
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2021-07-02 02:39:13 -06:00 |
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6f574abc9d
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clean up
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2021-07-02 02:07:22 -06:00 |
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e32e451e60
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update waveform view
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2021-07-02 02:03:32 -06:00 |
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5c59c97797
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build software project in same makefile as hardware project
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2021-07-02 02:03:32 -06:00 |
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4580631939
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clean up hdl directory
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2021-07-02 02:03:32 -06:00 |
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efd4cb6e48
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build test code into build directory
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2021-07-02 02:03:32 -06:00 |
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180f05fb0a
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shift to iverilog + gtkwave for simulation
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2021-07-02 02:03:32 -06:00 |
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a6a8b68c3b
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untracked files
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2021-05-03 22:13:26 -06:00 |
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d58661e289
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add more extensive memory test
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2020-11-14 23:36:23 -07:00 |
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6d39c01740
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fix testbench so both load and store work
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2020-11-14 23:21:33 -07:00 |
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f0166f1954
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load (word only) appears to be working
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2020-11-14 23:13:24 -07:00 |
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4a25ca6def
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fix issue of jumping to address 0
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2020-11-14 23:04:24 -07:00 |
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caf9a6f4f7
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separate .text and .data for instruction and data memory
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2020-11-10 00:19:42 -07:00 |
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32d0a2dcaa
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display more data to simplify verification
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2020-11-09 23:38:22 -07:00 |
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6e0d9c96a1
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passes quick test: beq, blt, bltu
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2020-11-09 20:01:25 -07:00 |
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82cbaba7e5
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I think this properly stalls for all implemented instructions so I don't need nops
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2020-11-07 00:47:20 -07:00 |
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1290418aa3
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properly flushes pipeline after jump
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2020-11-06 23:18:37 -07:00 |
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c98881c5d7
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passes quick test: slt, slti, sltu, sltiu
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2020-10-16 18:51:51 -06:00 |
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52a28d4e47
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passes quick test: sll, srl, sra
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2020-10-16 18:25:10 -06:00 |
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913ffb3af6
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passes quick test: slli, srli, srai
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2020-10-11 23:36:11 -06:00 |
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2c24c19a72
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passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
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2020-10-11 23:03:14 -06:00 |
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3fbd96ca27
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sub, and, or don't always work
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2020-10-03 13:49:14 -06:00 |
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24171412bd
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successfully using assembler to generate .hex rather than writing straight machine code
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2020-09-27 18:38:35 -06:00 |
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275f66bf24
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fix typo in core_tb.v assembly
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2020-09-27 18:07:12 -06:00 |
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2ad82e2b90
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add test assembly file
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2020-09-27 18:04:08 -06:00 |
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63ed8ace80
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initial commit. Non-working due to newly added MEM backpressure signal
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2020-09-27 16:04:16 -06:00 |
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