cpu/hdl
2020-11-14 23:21:33 -07:00
..
tb fix testbench so both load and store work 2020-11-14 23:21:33 -07:00
axi_lite_memory.v passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link 2020-10-11 23:03:14 -06:00
core.v load (word only) appears to be working 2020-11-14 23:13:24 -07:00
top.v initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00