Brendan Haines cc4101c1f8 prevent simulation from printing all writes to regfile

2021-07-03 21:02:48 -06:00

..

other_projects

clean up

2021-07-02 02:07:22 -06:00

tb

make sim will now fail if test hits fail state

2021-07-03 20:59:03 -06:00

.gitignore

shift to iverilog + gtkwave for simulation

2021-07-02 02:03:32 -06:00

core.v

prevent simulation from printing all writes to regfile

2021-07-03 21:02:48 -06:00