cpu/hdl
2021-07-02 02:03:32 -06:00
..
other_projects clean up hdl directory 2021-07-02 02:03:32 -06:00
tb build software project in same makefile as hardware project 2021-07-02 02:03:32 -06:00
.gitignore shift to iverilog + gtkwave for simulation 2021-07-02 02:03:32 -06:00
core.v load (word only) appears to be working 2020-11-14 23:13:24 -07:00
top.v initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00