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add test assembly file
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63ed8ace80
commit
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3
.gitmodules
vendored
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3
.gitmodules
vendored
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@ -0,0 +1,3 @@
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[submodule "asm/elf2hex"]
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path = asm/elf2hex
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url = https://github.com/sifive/elf2hex.git
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20
asm/Makefile
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20
asm/Makefile
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@ -0,0 +1,20 @@
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all: test.hex
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CC = riscv64-linux-gnu-gcc
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# CFLAGS = -march=rv32i -mabi=ilp32
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CFLAGS = -march=rv64i -mabi=lp64
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AS = riscv64-linux-gnu-as
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ASFLAGS = $(CFLAGS)
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LD = riscv64-linux-gnu-ld
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LDFLAGS = -T test.ld
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%.o: %.S
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$(AS) $(ASFLAGS) $^ -o $@
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%.elf: %.o
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$(LD) $(LDFLAGS) $^ -o $@
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test.hex: test.elf
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riscv64-linux-gnu-objdump -s $^ | sed -n '/0000/,$$p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' > $@
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36
asm/test.S
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36
asm/test.S
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@ -0,0 +1,36 @@
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.global _start
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.text
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_start:
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add x1, x0, x0
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add x2, x0, x0
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add x3, x0, x0
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add x4, x0, x0
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add x5, x0, x0
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add x6, x0, x0
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add x7, x0, x0
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add x8, x0, x0
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add x9, x0, x0
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add x10, x0, x0
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add x11, x0, x0
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add x12, x0, x0
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add x13, x0, x0
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add x14, x0, x0
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add x15, x0, x0
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add x16, x0, x0
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add x17, x0, x0
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add x18, x0, x0
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add x19, x0, x0
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add x20, x0, x0
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add x21, x0, x0
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add x22, x0, x0
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add x23, x0, x0
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add x24, x0, x0
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add x25, x0, x0
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add x26, x0, x0
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add x27, x0, x0
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add x28, x0, x0
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add x29, x0, x0
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add x30, x0, x0
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add x31, x0, x0
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.data
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12
asm/test.csv
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12
asm/test.csv
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@ -0,0 +1,12 @@
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test.elf: file format elf64-littleriscv
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Contents of section .text:
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0000 b3000000 33010000 b3010000 33020000 ....3.......3...
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0010 b3020000 33030000 b3030000 33040000 ....3.......3...
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0020 b3040000 33050000 b3050000 33060000 ....3.......3...
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0030 b3060000 33070000 b3070000 33080000 ....3.......3...
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0040 b3080000 33090000 b3090000 330a0000 ....3.......3...
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0050 b30a0000 330b0000 b30b0000 330c0000 ....3.......3...
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0060 b30c0000 330d0000 b30d0000 330e0000 ....3.......3...
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0070 b30e0000 330f0000 b30f0000 ....3.......
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BIN
asm/test.elf
Executable file
BIN
asm/test.elf
Executable file
Binary file not shown.
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asm/test.hex
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32
asm/test.hex
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@ -0,0 +1,32 @@
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b3000000
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33010000
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b3010000
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33020000
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b3020000
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33030000
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b3030000
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33040000
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b3040000
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33050000
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b3050000
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33060000
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b3060000
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33070000
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b3070000
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33080000
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b3080000
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33090000
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b3090000
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330a0000
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b30a0000
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330b0000
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b30b0000
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330c0000
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b30c0000
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330d0000
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b30d0000
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330e0000
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b30e0000
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330f0000
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b30f0000
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17
asm/test.ld
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17
asm/test.ld
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@ -0,0 +1,17 @@
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ENTRY(_start)
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MEMORY
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{
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ROM (rx) : ORIGIN = 0x00000000, LENGTH = 1024
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}
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SECTIONS
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{
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.text :
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{
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_text = .;
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*(.text*)
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*(.rodata*)
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_etext = .;
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} > ROM
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}
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29
hdl/core.v
29
hdl/core.v
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@ -30,6 +30,8 @@ reg [31:0] r_ex_s1, r_ex_s2, r_mem_s1, r_mem_s2;
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reg [31:0] r_mem_alu_out, r_wb_alu_out;
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reg r_mem_alu_zero;
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reg r_ex_jump;
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reg r_ex_store, r_mem_store;
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reg r_ex_load, r_mem_load;
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// IF
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reg s_if_halt;
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@ -64,6 +66,7 @@ reg [2:0] s_id_aluop;
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reg s_id_alu_seed;
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reg s_id_invalid;
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reg s_id_jump, s_id_branch;
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reg s_id_store, s_id_load;
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// RV32I / RV64I / RV32M
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localparam OP_LUI = 7'b0110111,
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@ -97,6 +100,8 @@ localparam ALUOP_ADD = 0,
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always @(*) begin
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s_id_halt = 0;
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s_id_invalid = 0;
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s_id_store = 0;
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s_id_load = 0;
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s_id_opcode = r_id_inst[6:0];
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s_id_rd = r_id_inst[11:7];
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@ -333,19 +338,19 @@ always @(posedge clk) begin
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// // stay halted forever
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// end else begin
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// IF
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if (!s_mem_bp) begin
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// if (!s_mem_bp) begin
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r_if_pc <= s_if_next_pc;
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end
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// end
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// ID
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if (!s_mem_bp) begin
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// if (!s_mem_bp) begin
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r_id_stall <= s_if_stall;
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r_id_pc <= r_if_pc;
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r_id_inst <= s_if_inst;
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end
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// end
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// EX
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if (!s_mem_bp) begin
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// if (!s_mem_bp) begin
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// TODO: also stall EX if taking branch
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r_ex_stall <= r_id_stall;
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r_ex_pc <= r_id_pc;
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@ -356,11 +361,13 @@ always @(posedge clk) begin
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r_ex_aluop <= s_id_aluop;
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r_ex_alu_seed <= s_id_alu_seed;
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r_ex_jump <= s_id_jump;
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end
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r_ex_store <= s_id_store;
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r_ex_load <= s_id_load;
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// end
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// MEM
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if (!s_mem_bp) begin
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// if (!s_mem_bp) begin
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r_mem_stall <= r_ex_stall;
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r_mem_pc <= r_ex_pc;
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r_mem_inst <= r_ex_inst;
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@ -369,15 +376,17 @@ always @(posedge clk) begin
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r_mem_s2 <= r_ex_s2;
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r_mem_alu_out <= s_ex_alu_out;
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r_mem_alu_zero <= s_ex_alu_zero;
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end
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r_mem_store <= r_ex_store;
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r_mem_load <= r_ex_load;
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// end
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// WB
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if (!s_mem_bp) begin
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// if (!s_mem_bp) begin
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r_wb_stall <= r_mem_stall;
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r_wb_pc <= r_mem_pc;
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r_wb_rd <= r_mem_rd;
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r_wb_alu_out <= r_mem_alu_out;
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end
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// end
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// Register File
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if (r_wb_rd != 0 && s_wb_write) begin
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