add test assembly file

This commit is contained in:
Brendan Haines 2020-09-27 18:04:08 -06:00
parent 63ed8ace80
commit 2ad82e2b90
8 changed files with 139 additions and 10 deletions

3
.gitmodules vendored Normal file
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@ -0,0 +1,3 @@
[submodule "asm/elf2hex"]
path = asm/elf2hex
url = https://github.com/sifive/elf2hex.git

20
asm/Makefile Normal file
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@ -0,0 +1,20 @@
all: test.hex
CC = riscv64-linux-gnu-gcc
# CFLAGS = -march=rv32i -mabi=ilp32
CFLAGS = -march=rv64i -mabi=lp64
AS = riscv64-linux-gnu-as
ASFLAGS = $(CFLAGS)
LD = riscv64-linux-gnu-ld
LDFLAGS = -T test.ld
%.o: %.S
$(AS) $(ASFLAGS) $^ -o $@
%.elf: %.o
$(LD) $(LDFLAGS) $^ -o $@
test.hex: test.elf
riscv64-linux-gnu-objdump -s $^ | sed -n '/0000/,$$p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' > $@

36
asm/test.S Normal file
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@ -0,0 +1,36 @@
.global _start
.text
_start:
add x1, x0, x0
add x2, x0, x0
add x3, x0, x0
add x4, x0, x0
add x5, x0, x0
add x6, x0, x0
add x7, x0, x0
add x8, x0, x0
add x9, x0, x0
add x10, x0, x0
add x11, x0, x0
add x12, x0, x0
add x13, x0, x0
add x14, x0, x0
add x15, x0, x0
add x16, x0, x0
add x17, x0, x0
add x18, x0, x0
add x19, x0, x0
add x20, x0, x0
add x21, x0, x0
add x22, x0, x0
add x23, x0, x0
add x24, x0, x0
add x25, x0, x0
add x26, x0, x0
add x27, x0, x0
add x28, x0, x0
add x29, x0, x0
add x30, x0, x0
add x31, x0, x0
.data

12
asm/test.csv Normal file
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@ -0,0 +1,12 @@
test.elf: file format elf64-littleriscv
Contents of section .text:
0000 b3000000 33010000 b3010000 33020000 ....3.......3...
0010 b3020000 33030000 b3030000 33040000 ....3.......3...
0020 b3040000 33050000 b3050000 33060000 ....3.......3...
0030 b3060000 33070000 b3070000 33080000 ....3.......3...
0040 b3080000 33090000 b3090000 330a0000 ....3.......3...
0050 b30a0000 330b0000 b30b0000 330c0000 ....3.......3...
0060 b30c0000 330d0000 b30d0000 330e0000 ....3.......3...
0070 b30e0000 330f0000 b30f0000 ....3.......
1 test.elf: file format elf64-littleriscv
2 Contents of section .text:
3 0000 b3000000 33010000 b3010000 33020000 ....3.......3...
4 0010 b3020000 33030000 b3030000 33040000 ....3.......3...
5 0020 b3040000 33050000 b3050000 33060000 ....3.......3...
6 0030 b3060000 33070000 b3070000 33080000 ....3.......3...
7 0040 b3080000 33090000 b3090000 330a0000 ....3.......3...
8 0050 b30a0000 330b0000 b30b0000 330c0000 ....3.......3...
9 0060 b30c0000 330d0000 b30d0000 330e0000 ....3.......3...
10 0070 b30e0000 330f0000 b30f0000 ....3.......

BIN
asm/test.elf Executable file

Binary file not shown.

32
asm/test.hex Normal file
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@ -0,0 +1,32 @@
b3000000
33010000
b3010000
33020000
b3020000
33030000
b3030000
33040000
b3040000
33050000
b3050000
33060000
b3060000
33070000
b3070000
33080000
b3080000
33090000
b3090000
330a0000
b30a0000
330b0000
b30b0000
330c0000
b30c0000
330d0000
b30d0000
330e0000
b30e0000
330f0000
b30f0000

17
asm/test.ld Normal file
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@ -0,0 +1,17 @@
ENTRY(_start)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 1024
}
SECTIONS
{
.text :
{
_text = .;
*(.text*)
*(.rodata*)
_etext = .;
} > ROM
}

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@ -30,6 +30,8 @@ reg [31:0] r_ex_s1, r_ex_s2, r_mem_s1, r_mem_s2;
reg [31:0] r_mem_alu_out, r_wb_alu_out;
reg r_mem_alu_zero;
reg r_ex_jump;
reg r_ex_store, r_mem_store;
reg r_ex_load, r_mem_load;
// IF
reg s_if_halt;
@ -64,6 +66,7 @@ reg [2:0] s_id_aluop;
reg s_id_alu_seed;
reg s_id_invalid;
reg s_id_jump, s_id_branch;
reg s_id_store, s_id_load;
// RV32I / RV64I / RV32M
localparam OP_LUI = 7'b0110111,
@ -97,6 +100,8 @@ localparam ALUOP_ADD = 0,
always @(*) begin
s_id_halt = 0;
s_id_invalid = 0;
s_id_store = 0;
s_id_load = 0;
s_id_opcode = r_id_inst[6:0];
s_id_rd = r_id_inst[11:7];
@ -333,19 +338,19 @@ always @(posedge clk) begin
// // stay halted forever
// end else begin
// IF
if (!s_mem_bp) begin
// if (!s_mem_bp) begin
r_if_pc <= s_if_next_pc;
end
// end
// ID
if (!s_mem_bp) begin
// if (!s_mem_bp) begin
r_id_stall <= s_if_stall;
r_id_pc <= r_if_pc;
r_id_inst <= s_if_inst;
end
// end
// EX
if (!s_mem_bp) begin
// if (!s_mem_bp) begin
// TODO: also stall EX if taking branch
r_ex_stall <= r_id_stall;
r_ex_pc <= r_id_pc;
@ -356,11 +361,13 @@ always @(posedge clk) begin
r_ex_aluop <= s_id_aluop;
r_ex_alu_seed <= s_id_alu_seed;
r_ex_jump <= s_id_jump;
end
r_ex_store <= s_id_store;
r_ex_load <= s_id_load;
// end
// MEM
if (!s_mem_bp) begin
// if (!s_mem_bp) begin
r_mem_stall <= r_ex_stall;
r_mem_pc <= r_ex_pc;
r_mem_inst <= r_ex_inst;
@ -369,15 +376,17 @@ always @(posedge clk) begin
r_mem_s2 <= r_ex_s2;
r_mem_alu_out <= s_ex_alu_out;
r_mem_alu_zero <= s_ex_alu_zero;
end
r_mem_store <= r_ex_store;
r_mem_load <= r_ex_load;
// end
// WB
if (!s_mem_bp) begin
// if (!s_mem_bp) begin
r_wb_stall <= r_mem_stall;
r_wb_pc <= r_mem_pc;
r_wb_rd <= r_mem_rd;
r_wb_alu_out <= r_mem_alu_out;
end
// end
// Register File
if (r_wb_rd != 0 && s_wb_write) begin