From 96295e0a7c94293047a8c2ba1fe779633bb7b03a Mon Sep 17 00:00:00 2001
From: Brendan Haines <brendan.haines@gmail.com>
Date: Thu, 9 Sep 2021 00:54:41 -0600
Subject: [PATCH] update README.md

---
 README.md | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 148c1b6..3e6a5ed 100644
--- a/README.md
+++ b/README.md
@@ -2,13 +2,18 @@
 
 # RISC-V CPU
 
-Harvard architecture
+Short Term To Do:
+* add stalls for memory access
+* use AXI for memory access
+* add tests for non-pipelined case
+* get C working (may depend on memory stalls)
 
 Desired features:
 * 1- or 5-stage pipeline selectable via parameter
 * AXI-lite Master for both instruction and data memory
-* 32, 64, or 128 bit word size
-* floating point support
+* 32, 64, (or 128?) bit word size
+* floating point
 * multiplication
 * division
 * instruction and data caches
+* JTAG debug probe