cpu/README.md

RISC-V CPU

Short Term To Do:

• add stalls for memory access
• use AXI for memory access
• add tests for non-pipelined case
• get C working (may depend on memory stalls)

Desired features:

• 1- or 5-stage pipeline selectable via parameter
• AXI-lite Master for both instruction and data memory
• 32, 64, (or 128?) bit word size
• floating point
• multiplication
• division
• instruction and data caches
• JTAG debug probe