Brendan Haines 8decf52443 make mem_data_rvalid a reg in tb		2021-07-03 21:17:42 -06:00
..
other_projects	clean up	2021-07-02 02:07:22 -06:00
tb	make mem_data_rvalid a reg in tb	2021-07-03 21:17:42 -06:00
.gitignore	shift to iverilog + gtkwave for simulation	2021-07-02 02:03:32 -06:00
core.v	prevent simulation from printing all writes to regfile	2021-07-03 21:02:48 -06:00