Commit Graph

18 Commits

Author SHA1 Message Date
d58661e289 add more extensive memory test 2020-11-14 23:36:23 -07:00
6d39c01740 fix testbench so both load and store work 2020-11-14 23:21:33 -07:00
f0166f1954 load (word only) appears to be working 2020-11-14 23:13:24 -07:00
4a25ca6def fix issue of jumping to address 0 2020-11-14 23:04:24 -07:00
caf9a6f4f7 separate .text and .data for instruction and data memory 2020-11-10 00:19:42 -07:00
32d0a2dcaa display more data to simplify verification 2020-11-09 23:38:22 -07:00
6e0d9c96a1 passes quick test: beq, blt, bltu 2020-11-09 20:01:25 -07:00
82cbaba7e5 I think this properly stalls for all implemented instructions so I don't need nops 2020-11-07 00:47:20 -07:00
1290418aa3 properly flushes pipeline after jump 2020-11-06 23:18:37 -07:00
c98881c5d7 passes quick test: slt, slti, sltu, sltiu 2020-10-16 18:51:51 -06:00
52a28d4e47 passes quick test: sll, srl, sra 2020-10-16 18:25:10 -06:00
913ffb3af6 passes quick test: slli, srli, srai 2020-10-11 23:36:11 -06:00
2c24c19a72 passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link 2020-10-11 23:03:14 -06:00
3fbd96ca27 sub, and, or don't always work 2020-10-03 13:49:14 -06:00
24171412bd successfully using assembler to generate .hex rather than writing straight machine code 2020-09-27 18:38:35 -06:00
275f66bf24 fix typo in core_tb.v assembly 2020-09-27 18:07:12 -06:00
2ad82e2b90 add test assembly file 2020-09-27 18:04:08 -06:00
63ed8ace80 initial commit. Non-working due to newly added MEM backpressure signal 2020-09-27 16:04:16 -06:00