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5cb8b7dd77
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start adding parallel ATA stuff
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2023-01-23 18:26:44 -07:00 |
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51103c378d
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update comment
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2023-01-23 18:26:14 -07:00 |
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71bc903f14
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ignore overrun at end of skidbuffer test
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2022-12-28 22:24:55 -07:00 |
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02db181281
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comment
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2022-12-28 22:07:28 -07:00 |
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f8c7460b29
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fix rdata output
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2022-12-07 20:03:13 -07:00 |
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e264602c1b
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Log levels are great but need more than one bit. oops
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2022-12-01 02:12:27 -07:00 |
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d3844129d3
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assert now catches X properly
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2022-12-01 02:09:51 -07:00 |
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cb7fbe84a5
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why does X look like 0 in my assertion for rdata?
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2022-12-01 02:04:17 -07:00 |
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e301d2c4d2
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move axil bridge
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2022-12-01 01:13:23 -07:00 |
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5d3d9b222f
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formatting
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2022-12-01 01:07:15 -07:00 |
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38a91579ec
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working assertion lib
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2022-12-01 01:03:23 -07:00 |
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ebc3b22ac7
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restructure testbenches and common code
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2022-12-01 00:45:57 -07:00 |
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