move axil bridge
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205
lib/axil_wb_bridge.sv
Normal file
205
lib/axil_wb_bridge.sv
Normal file
@@ -0,0 +1,205 @@
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// TODO: improve throughput. Currently limited to 1 write every 3 cycles and read every 2 cycles (plus wb slave latency)
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module axil_wb_bridge #(
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parameter ADDR_WIDTH = 8,
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parameter DATA_WIDTH = 32
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)(
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input logic clk,
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input logic reset,
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///// AXI4-Lite /////
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// Write address
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input logic axil_awvalid,
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output logic axil_awready,
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input logic [ADDR_WIDTH-1:0] axil_awaddr,
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input logic [2:0] axil_awprot,
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// Write data
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input logic axil_wvalid,
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output logic axil_wready,
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input logic [DATA_WIDTH-1:0] axil_wdata,
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input logic [DATA_WIDTH/8 - 1:0] axil_wstrb,
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// Write response
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output logic axil_bvalid,
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input logic axil_bready,
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output logic [1:0] axil_bresp,
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// Read address
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input logic axil_arvalid,
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output logic axil_arready,
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input logic [ADDR_WIDTH-1:0] axil_araddr,
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input logic [2:0] axil_arprot,
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// Read data
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output logic axil_rvalid,
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input logic axil_rready,
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output logic [DATA_WIDTH-1:0] axil_rdata,
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output logic [1:0] axil_rresp,
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///// Wishbone /////
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output logic [ADDR_WIDTH-1:0] wb_adr_o,
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input logic [DATA_WIDTH-1:0] wb_dat_i,
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output logic [DATA_WIDTH-1:0] wb_dat_o,
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output logic wb_we_o,
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output logic wb_sel_o,
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output logic wb_stb_o,
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input logic wb_ack_i,
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output logic wb_cyc_o
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);
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localparam AXIL_RESP_OKAY = 2'b00;
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// localparam AXIL_RESP_EXOKAY = 2'b01; // Only valid for full AXI, not AXI-Lite
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localparam AXIL_RESP_SLVERR = 2'b10;
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localparam AXIL_RESP_DECERR = 2'b11; // Indicates there is no slave at the transaction address
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localparam STATE_IDLE = 0;
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localparam STATE_READ = 1;
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localparam STATE_WRITE = 2;
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logic [ADDR_WIDTH-1:0] waddr;
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logic [ADDR_WIDTH-1:0] raddr;
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logic [DATA_WIDTH-1:0] wdata;
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logic [DATA_WIDTH-1:0] rdata;
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logic waddr_legal;
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logic raddr_legal;
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logic wdata_legal;
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logic waddr_valid = 0;
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logic raddr_valid = 0;
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logic wdata_valid = 0;
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logic rdata_valid = 0;
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logic w_complete = 0;
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logic [1:0] state_wb = STATE_IDLE;
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always_ff @(posedge clk) begin
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if (reset) begin
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waddr_valid <= 0;
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wdata_valid <= 0;
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w_complete <= 0;
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raddr_valid <= 0;
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rdata_valid <= 0;
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state_wb <= STATE_IDLE;
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end else begin
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// axil write address
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if (axil_awvalid && axil_awready) begin
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waddr <= axil_awaddr;
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waddr_valid <= 1;
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waddr_legal <= 1;
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// TODO: use write protection
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end
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// axil write data
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if (axil_wvalid && axil_wready) begin
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wdata <= axil_wdata;
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wdata_valid <= 1;
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if (&axil_wstrb) begin
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// wishbone only supports full width writes
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wdata_legal <= 1;
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// end else if (!|axil_wstrb) begin
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// // TODO: optionally discard and ignore access with axil_wstrb = 4'b0000
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end else begin
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// invalid write strobe combination
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wdata_legal <= 0;
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end
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end
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if (
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((axil_wvalid && axil_wready) || wdata_valid) &&
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((axil_awvalid && axil_awready) || waddr_valid) &&
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!w_complete
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// TODO: check for wdata_legal (and combinatorial wdata_legal)
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) begin
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if (state_wb == STATE_IDLE) begin
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state_wb <= STATE_WRITE;
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end
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end
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// axil write response
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if (axil_bvalid && axil_bready) begin
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// reset write logic for next transfer
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waddr_valid <= 0;
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wdata_valid <= 0;
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w_complete <= 0;
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end
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// axil read address
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if (axil_arvalid && axil_arready) begin
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raddr <= axil_araddr;
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raddr_valid <= 1;
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raddr_legal <= 1;
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// TODO: use read protection
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if (state_wb == STATE_IDLE) begin
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// if write and read arrive on the same cycle, read takes priority
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state_wb <= STATE_READ;
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end
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end
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// axil read data
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if (axil_rvalid && axil_rready) begin
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// read is complete. Get ready for next read
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raddr_valid <= 0;
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rdata_valid <= 0;
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end
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// wb
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case (state_wb)
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STATE_IDLE: begin
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// do nothing
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end
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STATE_WRITE: begin
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if (wb_cyc_o && wb_sel_o && wb_stb_o && wb_ack_i) begin
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w_complete <= 1;
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state_wb <= STATE_IDLE;
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// TODO: switch directly to STATE_READ if we can
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end
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end
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STATE_READ: begin
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if (wb_cyc_o && wb_sel_o && wb_stb_o && wb_ack_i) begin
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rdata <= wb_dat_i;
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rdata_valid <= 1;
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state_wb <= STATE_IDLE;
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// TODO: switch directly to STATE_WRITE if we can
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// This will also ensure continuous reads don't inhibit all writes
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end
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end
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default: begin
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// bh_assert_equal(state_wb, 0, "Wishbone master encountered unknown state");
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state_wb <= STATE_IDLE;
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end
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endcase
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end
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end
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always_comb begin
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// axil write address
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axil_awready = !waddr_valid;
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// axil write data
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axil_wready = !wdata_valid;
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// axil write response
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axil_bvalid = waddr_valid && wdata_valid && w_complete;
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axil_bresp = (waddr_legal && wdata_legal) ? AXIL_RESP_OKAY : AXIL_RESP_SLVERR;
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// axil read address
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axil_arready = !raddr_valid;
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// axil read data
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axil_rvalid = rdata_valid;
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axil_rresp = raddr_legal ? AXIL_RESP_OKAY : AXIL_RESP_SLVERR;
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// wishbone
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wb_we_o = state_wb == STATE_WRITE;
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wb_dat_o = wdata;
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wb_adr_o = (state_wb == STATE_WRITE) ? waddr : raddr;
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wb_cyc_o = state_wb == STATE_WRITE || state_wb == STATE_READ;
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wb_sel_o = 1; // TODO: figure out if this is right
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wb_stb_o = 1; // TODO: figure out if this is right
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end
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endmodule
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105
lib/tb/axil_wb_bridge_tb.sv
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105
lib/tb/axil_wb_bridge_tb.sv
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@@ -0,0 +1,105 @@
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`include "bh_assert.sv"
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`timescale 1ns/1ps
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import bh_assert::bh_assert_equal;
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import bh_assert::bh_assert_stats;
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module axil_wb_bridge_tb();
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parameter ADDR_WIDTH = 8;
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parameter DATA_WIDTH = 32;
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logic clk = 0;
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logic reset = 1;
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logic axil_awvalid;
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logic axil_awready;
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logic [ADDR_WIDTH-1:0] axil_awaddr;
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logic [2:0] axil_awprot;
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logic axil_wvalid;
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logic axil_wready;
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logic [DATA_WIDTH-1:0] axil_wdata;
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logic [DATA_WIDTH/8 - 1:0] axil_wstrb;
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logic axil_bvalid;
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logic axil_bready;
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logic [1:0] axil_bresp;
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logic axil_arvalid;
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logic axil_arready;
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logic [ADDR_WIDTH-1:0] axil_araddr;
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logic [2:0] axil_arprot;
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logic axil_rvalid;
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logic axil_rready;
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logic [DATA_WIDTH-1:0] axil_rdata;
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logic [2:0] axil_rresp;
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logic [ADDR_WIDTH-1:0] wb_adr_o;
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logic [DATA_WIDTH-1:0] wb_dat_i;
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logic [DATA_WIDTH-1:0] wb_dat_o;
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logic wb_we_o;
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logic wb_sel_o;
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logic wb_stb_o;
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logic wb_ack_i;
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logic wb_cyc_o;
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axil_wb_bridge #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)
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) dut(
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.clk(clk),
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.reset(reset),
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///// AXI4-Lite /////
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// Write address
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.axil_awvalid(axil_awvalid),
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.axil_awready(axil_awready),
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.axil_awaddr(axil_awaddr),
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.axil_awprot(axil_awprot),
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// Write data
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.axil_wvalid(axil_wvalid),
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.axil_wready(axil_wready),
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.axil_wdata(axil_wdata),
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.axil_wstrb(axil_wstrb),
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// Write response
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.axil_bvalid(axil_bvalid),
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.axil_bready(axil_bready),
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.axil_bresp(axil_bresp),
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// Read address
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.axil_arvalid(axil_arvalid),
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.axil_arready(axil_arready),
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.axil_araddr(axil_araddr),
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.axil_arprot(axil_arprot),
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// Read data
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.axil_rvalid(axil_rvalid),
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.axil_rready(axil_rready),
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.axil_rdata(axil_rdata),
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.axil_rresp(axil_rresp),
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///// Wishbone /////
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.wb_adr_o(wb_adr_o),
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.wb_dat_i(wb_dat_i),
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.wb_dat_o(wb_dat_o),
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.wb_we_o(wb_we_o),
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.wb_sel_o(wb_sel_o),
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.wb_stb_o(wb_stb_o),
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.wb_ack_i(wb_ack_i),
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.wb_cyc_o(wb_cyc_o)
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);
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always #5 clk <= !clk;
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initial begin
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#10
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bh_assert_stats();
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$finish;
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end
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endmodule
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@@ -60,6 +60,7 @@ module skidbuffer_tb();
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end
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end
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#10
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bh_assert_stats();
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$finish;
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end
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