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15 lines
363 B
Markdown
15 lines
363 B
Markdown
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# RISC-V CPU
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Harvard architecture
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Desired features:
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* 1- or 5-stage pipeline selectable via parameter
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* AXI-lite Master for both instruction and data memory
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* 32, 64, or 128 bit word size
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* floating point support
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* multiplication
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* division
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* instruction and data caches
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